公开(公告)号：EP1763080A2

公开(公告)日：2007-03-14

申请号：EP06120354.3

申请日：2006-09-08

Applicant: Saifun Semiconductors Ltd.

Inventor： Lusky, Eli ,  Eitan, Boaz

IPC: H01L27/115 ,  H01L21/8247

CPC classification number: H01L27/11568 ,  H01L27/115

Abstract: A non-volatile memory device includes a plurality of word line areas each separated from its neighbor by a contact area, an oxide-nitride-oxide (ONO) layer within the word line areas and at least partially within the contact areas and protective elements generated when spacers are formed in the periphery area, to protect silicon under the ONO layer in the contact areas A non-volatile memory device includes a plurality of word line areas each separated from is neighbor by a contact area and bit line oxides whose height is at least a quarter of the distance between neighboring bit line oxides.

Abstract translation: 非易失性存储器件包括多个字线区域，每个字线区域与其相邻部分由接触区域分开，字线区域内的氧化物 - 氧化物 - 氧化物（ONO）层和至少部分地在接触区域内产生的保护元件 当在周边区域中形成间隔物时，为了保护接触区域内的ONO层下的硅，非易失性存储器件包括多个字线区域，每个字线区域与接触区域相邻，位线高度位于 相邻位线氧化物之间的距离最少四分之一。

公开(公告)号：EP1755127A2

公开(公告)日：2007-02-21

申请号：EP06118949.4

申请日：2006-08-15

Applicant: Saifun Semiconductors Ltd.

Inventor： Lusky, Eli ,  Eitan, Boaz

IPC: G11C16/16

CPC classification number: G11C16/16 ,  G11C16/344 ,  G11C16/3445

Abstract: A method includes determining groups of rows to erase together in order to minimize the margin loss associated with bake after a large number of program and erasure cycles. The method alternatively includes determining groups of rows to erase together to minimize the width of a resultant erase threshold voltage distribution, erasing the groups together, stopping erasure of a group when the group is erase verified and performing the step of erasing on those groups which were not previously erase verified.

Abstract translation: 一种方法包括确定要一起擦除的行组，以便在大量编程和擦除循环之后最小化与烘烤相关的裕度损失。 所述方法或者包括确定一组行以擦除在一起以最小化所得到的擦除阈值电压分布的宽度，擦除组在一起，当组被擦除验证时停止擦除组，并且执行擦除步骤 以前没有擦除验证。

公开(公告)号：EP1227498A3

公开(公告)日：2004-06-30

申请号：EP02250357.7

申请日：2002-01-18

Applicant: Saifun Semiconductors Ltd.

Inventor： Eliyahu, Ron ,  Maayan, Eduardo ,  Bloom, Ilan ,  Eitan, Boaz

IPC: G11C16/04 ,  G11C16/10 ,  G11C16/34

CPC classification number: G11C16/3427 ,  G11C11/5671 ,  G11C16/0475 ,  G11C16/10 ,  G11C16/14 ,  G11C16/3418

Abstract: A method for operating an electrically erasable programmable read only memory (EEPROM) array includes providing an array including a multiplicity of memory cells, wherein each memory cell is connected to a word line and to two bit lines, selecting one of the memory cells, and erasing a bit of the selected memory cell while applying an inhibit word line voltage to a gate of an unselected memory cell. An EEPROM array is also described, the array including a multiplicity of NROM memory cells, wherein each memory cell is connected to a word line and to two bit lines, and wherein each NROM cell is individually erasable and individually programmable without significantly disturbing unselected cells.

公开(公告)号：EP1211731A2

公开(公告)日：2002-06-05

申请号：EP01123177.6

申请日：2001-09-27

Applicant: Saifun Semiconductors Ltd.

Inventor： Maayan, Eduardo ,  Eitan, Boaz

IPC: H01L27/115

CPC classification number: H01L27/11568 ,  G11C7/18 ,  G11C11/5671 ,  G11C16/0475 ,  G11C16/0491 ,  G11C16/24 ,  H01L27/112 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

Abstract: A memory array includes a first plurality of metal bit lines, a second plurality of diffusion bit lines and a third plurality of select transistors. There are more than two diffusion bit lines per metal bit line.

Abstract translation: 存储器阵列包括第一多个金属位线，第二多个扩散位线和第三多个选择晶体管。 每个金属位线有两个以上的扩散位线。

公开(公告)号：EP1096505A1

公开(公告)日：2001-05-02

申请号：EP00309314.3

申请日：2000-10-23

Applicant: Saifun Semiconductors Ltd.

Inventor： Eitan, Boaz

IPC: G11C16/04 ,  H01L29/792 ,  H01L27/115

CPC classification number: H01L29/66833 ,  G11C11/5671 ,  G11C16/0475 ,  H01L29/792

Abstract: A method of creating a nitride, programmable read only memory (NROM) cell includes the step of decoupling injection of channel hot electrons into a charge trapping layer of the NROM cell from injection of non-channel electrons into the charge trapping layer. The step of decoupling can include the step of minimizing the injection of the non-channel electrons into the charge trapping layer. Alternatively, it includes the step of minimizing the generation of the non-channel electrons. The present invention includes cells which have minimal injection of non-channel electrons therein.

Abstract translation: 创建氮化物可编程只读存储器（NROM）单元的方法包括将通道热电子注入到NROM单元的电荷捕获层中以将非沟道电子注入到电荷捕获层中的步骤。 去耦合的步骤可以包括使非沟道电子注入到电荷俘获层中最小化的步骤。 或者，它包括最小化非沟道电子的产生的步骤。 本发明包括其中非通道电子注入最少的电池。

公开(公告)号：EP1073120A2

公开(公告)日：2001-01-31

申请号：EP00305940.9

申请日：2000-07-13

Applicant: Saifun Semiconductors Ltd

Inventor： Eitan, Boaz

IPC: H01L27/115 ,  H01L29/792 ,  H01L21/8247

CPC classification number: H01L27/11568 ,  H01L21/28282 ,  H01L21/3143 ,  H01L21/32 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/115 ,  H01L27/11517 ,  H01L29/792 ,  Y10S438/954

Abstract: A method of fabricating a nitride read only memory (NROM) chip creates an oxide-nitride-oxide (ONO) layer (18, 17, 20) on a substrate and etches the ONO layer within the memory portion of the chip into columns. Bit lines (12) are implanted between columns after which bit line oxides (50) are generated on top of the bit lines with the thickness of the bit line oxides being independent of the thickness of the bottom oxide. The thickness of a gate oxide layer in a periphery portion of the chip is also relatively independent of the thicknesses of the other oxides. Finally, rows of polysilicon or polysilicide (60) are formed perpendicular to and on top of the bit line oxides and the ONO columns.

Abstract translation: 制造氮化物只读存储器（NROM）芯片的方法在衬底上产生氧化物 - 氧化物 - 氧化物（ONI）层（18,17,20），并将芯片的存储器部分内的ONO层蚀刻成列。 位线（12）注入列之后，位线氧化物（50）在位线顶部产生，位线氧化物的厚度与底部氧化物的厚度无关。 芯片周边部分的栅极氧化物层的厚度也相对独立于其它氧化物的厚度。 最后，多晶硅或聚硅化物（60）的行垂直于位线氧化物和ONO柱形成。

公开(公告)号：EP1746645A2

公开(公告)日：2007-01-24

申请号：EP06117424.9

申请日：2006-07-18

Applicant: Saifun Semiconductors Ltd.

Inventor： Eitan, Boaz ,  Bloom, Ilan ,  Irani, Rustom

IPC: H01L21/8246 ,  H01L27/115

CPC classification number: H01L27/115 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/28123 ,  H01L21/31144 ,  H01L21/32139 ,  H01L27/0207 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/792 ,  H01L29/7923 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A non-volatile memory array (30) has word lines (32) spaced a sub-F (sub-minimum feature size F) width apart and bit lines generally perpendicular to the word lines. The present invention also includes a method for word-line patterning of a non-volatile memory array which includes generating sub-F word lines from mask generated elements with widths of at least a minimum feature size F.

Abstract translation: 非易失性存储器阵列（30）具有间隔开的子F（子最小特征尺寸F）宽度的字线（32），并且大致垂直于字线的位线。 本发明还包括用于非易失性存储器阵列的字线图案化的方法，其包括从具有至少最小特征尺寸F的宽度的掩模生成元素生成子F字线。

公开(公告)号：EP1227501A3

公开(公告)日：2003-07-30

申请号：EP01309290.3

申请日：2001-11-01

Applicant: Saifun Semiconductors Ltd.

Inventor： Avni, Dror ,  Eitan, Boaz

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/14

CPC classification number: G11C11/5671 ,  G11C16/0475 ,  G11C16/10 ,  G11C16/14 ,  G11C16/28 ,  G11C16/3468 ,  G11C16/3481

Abstract: A method for programming and erasing a memory array includes the step of adapting programming or erase pulses to the current state of the memory array. In one embodiment, the step of adapting includes the steps of determining the voltage level of the programming pulse used to program a fast bit of the memory array and setting an initial programming level of the memory array to a level in the general vicinity of the programming level of the fast bit. For erasure, the method includes the steps of determining erase conditions of the erase pulse used to erase a slowly erasing bit of said memory array and setting initial erase conditions of said memory array to the general vicinity of said erase conditions of said slowly erasing bit. In another embodiment of the array, the step of adapting includes the steps of measuring the current threshold level of a bit to within a given range and selecting an incremental voltage level of a next programming or erase pulse for the bit in accordance with the measured current threshold level.

公开(公告)号：EP1091418A3

公开(公告)日：2003-06-18

申请号：EP00308781.4

申请日：2000-10-05

Applicant: Saifun Semiconductors Ltd

Inventor： Eitan, Boaz

IPC: H01L29/792 ,  G11C11/56 ,  G11C16/04 ,  H01L21/336 ,  H01L21/8246

CPC classification number: H01L27/11568 ,  G11C11/5671 ,  G11C16/0475 ,  H01L21/26586 ,  H01L27/115 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7923

Abstract: A nitride programmable read only memory (NROM) cell has an oxide-nitride-oxide (ONO) layer (109, 110, 111) over at least a channel (100) and a pocket implant (120) self-aligned to at least one bit line junction (102). The cell also includes at least one area of hot electron injection within the ONO layer and over the pocket implant and at least one area of hot hole injection generally self-aligned to the area of hot electron injection.

公开(公告)号：EP1061580A3

公开(公告)日：2001-05-30

申请号：EP00305161.2

申请日：2000-06-19

Applicant: Saifun Semiconductors Ltd.

Inventor： Eitan, Boaz ,  Bloom, Ilan

IPC: H01L27/02

CPC classification number: H01L27/0266 ,  H01L21/3065 ,  H01L21/31116 ,  H01L27/0251

Abstract: A protection device which is active during the manufacturing process of a semiconductor chip includes a protection transistor (52) and an antenna (55). The protection transistor is connected between a metal line (40) having devices to be protected electrically connected thereto and a ground supply (41), where the metal line is connected to devices (50) to be protected. The antenna is formed of the same metal layer as the metal line and controls the operation of the protection transistor during the manufacturing process. The antenna (55) is connected to a gate (G) of the protection transistor. Optionally, there is a metal ring (112, Fig. 7) around the antenna which is connected to a drain (D) of the protection transistor via the same metal layer as the metal line. During normal operation of the chip, the protection transistor is either active for other purposes or is turned off. Turning off is provided either by a line formed of a second metal layer that is connected between the antenna and ground, or by a reversed biased diode (118) and a parallel capacitor (120) that are connected between the gate of the protection transistor and ground. The present invention includes the method of manufacturing the protection device.