公开(公告)号：EP3948868B1

公开(公告)日：2024-06-05

申请号：EP19949340.4

申请日：2019-10-18

IPC分类号： G11C16/34 ,  G11C16/08 ,  G11C16/10 ,  G11C11/56

CPC分类号： G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C2211/562120130101 ,  G11C16/3459 ,  G11C11/5628 ,  G11C16/3481

公开(公告)号：EP2304730A1

公开(公告)日：2011-04-06

申请号：EP09771201.2

申请日：2009-06-26

申请人： Sandisk 3D LLC

发明人： SCHEUERLEIN, Roy, E. ,  YAN, Tianhong

IPC分类号： G11C13/00

CPC分类号： G11C13/0007 ,  G11C13/0064 ,  G11C13/0069 ,  G11C16/3481 ,  G11C2013/0078 ,  G11C2213/32 ,  G11C2213/34 ,  G11C2213/71 ,  G11C2213/72

摘要： A storage system includes a substrate, control circuitry on the substrate, a three dimensional memory array (above the substrate) that includes a plurality of reversible resistance-switching elements, and circuits for limiting the SET current for the reversible resistance-switching elements. The memory cell is SET in a reverse biased fashion.

公开(公告)号：EP1225596B1

公开(公告)日：2007-02-14

申请号：EP01309289.5

申请日：2001-11-01

申请人： Saifun Semiconductors Ltd.

发明人： Bloom, Ilan ,  Maayan, Eduardo ,  Eitan, Boaz

IPC分类号： G11C16/10

CPC分类号： G11C11/5671 ,  G11C16/0475 ,  G11C16/10 ,  G11C16/14 ,  G11C16/28 ,  G11C16/3468 ,  G11C16/3481 ,  G11C2211/5634

公开(公告)号：EP1158530B1

公开(公告)日：2004-08-25

申请号：EP01109448.9

申请日：1993-06-25

申请人： FUJITSU LIMITED

发明人： Akaogi, Takao ,  Takashina, Nobuaki ,  Kasa, Yasushi ,  Itano, Kiyoshi ,  Kawashima, Hiromi ,  Yamashita, Minoru ,  Kawamura, Shouichi

IPC分类号： G11C16/26 ,  G11C16/08

CPC分类号： G11C29/80 ,  G11C5/145 ,  G11C7/067 ,  G11C8/00 ,  G11C8/08 ,  G11C8/10 ,  G11C16/04 ,  G11C16/0416 ,  G11C16/08 ,  G11C16/10 ,  G11C16/107 ,  G11C16/12 ,  G11C16/16 ,  G11C16/26 ,  G11C16/30 ,  G11C16/3404 ,  G11C16/3409 ,  G11C16/3436 ,  G11C16/3445 ,  G11C16/3459 ,  G11C16/3472 ,  G11C16/3481 ,  G11C29/028 ,  G11C29/34 ,  G11C29/46 ,  G11C29/50 ,  G11C29/50004 ,  G11C29/802 ,  G11C29/82 ,  G11C29/88 ,  G11C2029/5004

摘要： A semiconductor memory device having electrically erasable nonvolatile memory cells to and from which data is automatically written and erased according to an internal algorithm incorporated in said semiconductor memory device. The allowable value of write or erase operations is determined according to the internal algorithm, which is variable. Thus, a device embodying the present invention can carry out a delivery test with "n" rewrite operations at the most, and taking into account deterioration due to an increase in the number of rewrite operations, can guarantee the maximum number of rewrite operations N (N>n) possible by a user.

公开(公告)号：EP1225596A3

公开(公告)日：2003-07-23

申请号：EP01309289.5

申请日：2001-11-01

申请人： Saifun Semiconductors Ltd.

发明人： Bloom, Ilan ,  Maayan, Eduardo ,  Eitan, Boaz

IPC分类号： G11C16/10

CPC分类号： G11C11/5671 ,  G11C16/0475 ,  G11C16/10 ,  G11C16/14 ,  G11C16/28 ,  G11C16/3468 ,  G11C16/3481 ,  G11C2211/5634

摘要： A method for programming a reference cell of a memory array includes the steps of programming the reference cell with large programming steps until a threshold voltage level of the reference cell is above an interim target level and programming said reference cell with small programming steps until the threshold voltage level is above a final target level.

公开(公告)号：EP1158534A3

公开(公告)日：2002-08-14

申请号：EP01109454.7

申请日：1993-06-25

申请人： FUJITSU LIMITED

发明人： Akaogi, Takao ,  Takashina, Nobuaki ,  Kasa, Yasushi ,  Itano, Kiyoshi ,  Kawashima, Hiromi ,  Yamashita, Minoru ,  Kawamura, Shouichi

IPC分类号： G11C16/30 ,  G11C16/12

CPC分类号： G11C29/80 ,  G11C5/145 ,  G11C7/067 ,  G11C8/00 ,  G11C8/08 ,  G11C8/10 ,  G11C16/04 ,  G11C16/0416 ,  G11C16/08 ,  G11C16/10 ,  G11C16/107 ,  G11C16/12 ,  G11C16/16 ,  G11C16/26 ,  G11C16/30 ,  G11C16/3404 ,  G11C16/3409 ,  G11C16/3436 ,  G11C16/3445 ,  G11C16/3459 ,  G11C16/3472 ,  G11C16/3481 ,  G11C29/028 ,  G11C29/34 ,  G11C29/46 ,  G11C29/50 ,  G11C29/50004 ,  G11C29/802 ,  G11C29/82 ,  G11C29/88 ,  G11C2029/5004

摘要： A semiconductor memory device (801) having a first terminal (805) for receiving a normal voltage (Vcc) from a normal voltage supply means, and a second terminal (806) for receiving a high voltage (Vpp) from a high-voltage supply means (802), the high voltage (Vpp) being required to write or erase data and higher than the normal voltage (Vcc) required to read data. The semiconductor memory device comprises a third terminal (807) for providing the high-voltage supply means (802) with a control signal that controls the supply of said high voltage. In this way, the two voltage supplies become easy to use and operable like a single supply means.

摘要翻译： 一种半导体存储器件（801），具有用于从正常电压供应装置接收正常电压（Vcc）的第一端子（805）以及用于从高压电源（Vpp）接收高电压（Vpp）的第二端子（806） 意味着（802），写入或擦除数据所需的高电压（Vpp）高于读取数据所需的正常电压（Vcc）。 该半导体存储器件包括用于向高压供电装置（802）提供控制所述高电压的供应的控制信号的第三端子（807）。 这样，两个电压供应变得易于使用并且可以像单个供应装置那样操作。

公开(公告)号：EP1158531A3

公开(公告)日：2002-08-14

申请号：EP01109450.5

申请日：1993-06-25

申请人： FUJITSU LIMITED

发明人： Akaogi, Takao ,  Takashina, Nobuaki ,  Kasa, Yasushi ,  Itano, Kiyoshi ,  Kawashima, Hiromi ,  Yamashita, Minoru ,  Kawamura, Shouichi

IPC分类号： G11C16/34

CPC分类号： G11C29/80 ,  G11C5/145 ,  G11C7/067 ,  G11C8/00 ,  G11C8/08 ,  G11C8/10 ,  G11C16/04 ,  G11C16/0416 ,  G11C16/08 ,  G11C16/10 ,  G11C16/107 ,  G11C16/12 ,  G11C16/16 ,  G11C16/26 ,  G11C16/30 ,  G11C16/3404 ,  G11C16/3409 ,  G11C16/3436 ,  G11C16/3445 ,  G11C16/3459 ,  G11C16/3472 ,  G11C16/3481 ,  G11C29/028 ,  G11C29/34 ,  G11C29/46 ,  G11C29/50 ,  G11C29/50004 ,  G11C29/802 ,  G11C29/82 ,  G11C29/88 ,  G11C2029/5004

摘要： A semiconductor memory device having a plurality of word lines (WLs), a plurality of bit lines (BLs), and nonvolatile memory cells (MCs) formed of a MIS transistor disposed at each intersection of the word lines and bit lines. A threshold voltage of each MIS transistor is externally electrically controllable. A write circuit (106) is provided for writing data to a memory cell located at an intersection of selected ones of the word lines and bit lines, and a sense amplifier (107) is provided for reading data out of the memory cells. The invention provides means for controlling each word line such that a drain current of a memory cell transistor connected to a word line is lower than a channel current thereof, when writing data to the cell transistor, to increase the threshold voltage of the memory cell transistor higher than the potential of an unselected word line.

公开(公告)号：EP1227501A2

公开(公告)日：2002-07-31

申请号：EP01309290.3

申请日：2001-11-01

申请人： Saifun Semiconductors Ltd.

发明人： Avni, Dror ,  Eitan, Boaz

IPC分类号： G11C16/34 ,  G11C16/10

CPC分类号： G11C11/5671 ,  G11C16/0475 ,  G11C16/10 ,  G11C16/14 ,  G11C16/28 ,  G11C16/3468 ,  G11C16/3481

摘要： A method for programming and erasing a memory array includes the step of adapting programming or erase pulses to the current state of the memory array. In one embodiment, the step of adapting includes the steps of determining the voltage level of the programming pulse used to program a fast bit of the memory array and setting an initial programming level of the memory array to a level in the general vicinity of the programming level of the fast bit. For erasure, the method includes the steps of determining erase conditions of the erase pulse used to erase a slowly erasing bit of said memory array and setting initial erase conditions of said memory array to the general vicinity of said erase conditions of said slowly erasing bit. In another embodiment of the array, the step of adapting includes the steps of measuring the current threshold level of a bit to within a given range and selecting an incremental voltage level of a next programming or erase pulse for the bit in accordance with the measured current threshold level.

摘要翻译： 用于编程和擦除存储器阵列的方法包括将编程或擦除脉冲适配到存储器阵列的当前状态的步骤。 在一个实施例中，适配步骤包括以下步骤：确定用于对存储器阵列的快速位进行编程的编程脉冲的电压电平，并将存储器阵列的初始编程电平设置为程序的一般附近的电平 水平的快速位。 为了擦除，该方法包括以下步骤：确定用于擦除所述存储器阵列的缓慢擦除位的擦除脉冲的擦除条件，并将所述存储器阵列的初始擦除条件设置为所述缓慢擦除位的所述擦除条件的附近。 在阵列的另一实施例中，适配步骤包括以下步骤：将位的电流阈值电平测量到给定范围内，并根据测量的电流选择位的下一个编程或擦除脉冲的增量电压电平 门限等级。

公开(公告)号：EP0600151B1

公开(公告)日：2001-11-07

申请号：EP93110192.7

申请日：1993-06-25

申请人： FUJITSU LIMITED

发明人： Akaogi, Takao ,  Takashina, Nobuaki ,  Kasa, Yasushi ,  Itano, Kiyoshi ,  Kawashima, Hiromi ,  Yamashita, Minoru ,  Kawamura, Shouichi

IPC分类号： G06F11/20 ,  G11C16/06

CPC分类号： G11C29/80 ,  G11C5/145 ,  G11C7/067 ,  G11C8/00 ,  G11C8/08 ,  G11C8/10 ,  G11C16/04 ,  G11C16/0416 ,  G11C16/08 ,  G11C16/10 ,  G11C16/107 ,  G11C16/12 ,  G11C16/16 ,  G11C16/26 ,  G11C16/30 ,  G11C16/3404 ,  G11C16/3409 ,  G11C16/3436 ,  G11C16/3445 ,  G11C16/3459 ,  G11C16/3472 ,  G11C16/3481 ,  G11C29/028 ,  G11C29/34 ,  G11C29/46 ,  G11C29/50 ,  G11C29/50004 ,  G11C29/802 ,  G11C29/82 ,  G11C29/88 ,  G11C2029/5004

摘要： A semiconductor memory device having electrically erasable nonvolatile memory cells to and from which data is automatically written and erased according to an internal algorithm incorporated in said semiconductor memory device. The allowable value of write or erase operations is determined according to the internal algorithm, which is variable. Thus, a device embodying the present invention can carry out a delivery test with "n" rewrite operations at the most, and taking into account deterioration due to an increase in the number of rewrite operations, can guarantee the maximum number of rewrite operations N (N>n) possible by a user.

公开(公告)号：EP1020870A1

公开(公告)日：2000-07-19

申请号：EP99302170.8

申请日：1999-03-19

申请人： Macronix International Co., Ltd.

发明人： Lin, Chin Hsi

IPC分类号： G11C11/56 ,  G11C16/06

CPC分类号： G11C16/3459 ,  G11C8/14 ,  G11C11/5621 ,  G11C11/5628 ,  G11C16/08 ,  G11C16/34 ,  G11C16/3468 ,  G11C16/3481 ,  G11C2211/5621 ,  G11C2211/5624 ,  G11C2211/5645

摘要： A method and device are provided for programming multiple levels of voltage states in a memory cell. A program and verify memory cell device includes a memory cell coupled with at least one dummy cell, the devices sharing common drain, gate, and source nodes. The threshold voltage of each dummy cell is set to a target threshold level for programming the memory cell. A stair-step sequence of pulses is preferably used to program and verify the memory cell. A constant current source can also be coupled between the source node and the ground. The programming steps for this device preferably include applying a high voltage to the drain and gate nodes, and coupling the source to a certain intermediate voltage level while starting the program pulse, then establishing a constant current at the source to pull it from high to a low level, and then applying program and verify pulses at the memory cell gate. A self convergence memory cell device includes the parallel connected memory and dummy cells above, but with at least one current sensing device coupled between the dummy cell and the drain. The programming steps for this device preferably include applying a high voltage to the drain and gate nodes, and coupling the source to a certain fixed voltage level while starting the program pulse, then establishing a constant current at the source to pull it from high to a low level, and then using the current sensing device to pull down the drain when a certain dummy cell current is reached upon subsequent application of programming pulses.