公开(公告)号：EP2453361A1

公开(公告)日：2012-05-16

申请号：EP11188771.7

申请日：2011-11-11

申请人： Samsung Electronics Co., Ltd ,  SNU R&DB Foundation

发明人： Lee, Hyuk Jae ,  Kwon, Kwon Taek ,  Jung, Seok Yoon ,  Kim, Kyu Dong ,  Woo, Deum Ji

IPC分类号： G06F13/362

CPC分类号： G06F13/3625

摘要： A bus arbitration apparatus and method are provided. A plurality of masters may be classified into master types based on master characteristics, and bus arbitration may be performed. Thus, it is possible to prevent a bus from being distributed to a predetermined master, and it is possible to improve overall performance of a bus system by solving a problem of unbalanced distribution of performance between the plurality of masters.

摘要翻译： 提供一种总线仲裁装置和方法。 可以基于主特性将多个主机分类为主机类型，并且可以执行总线仲裁。 因此，可以防止总线分配到预定的主机，并且可以通过解决多个主机之间的性能不均衡分配的问题来改善总线系统的总体性能。

公开(公告)号：EP2315180A2

公开(公告)日：2011-04-27

申请号：EP10178164.9

申请日：2010-09-22

申请人： Samsung Electronics Co., Ltd.

发明人： Woo, Sang Oak ,  Jung, Seok Yoon ,  Kwon, Kwon Taek

IPC分类号： G06T15/00

CPC分类号： G06T15/005 ,  G06T2210/12

摘要： A tile based rendering apparatus and method is provided. The rendering method may be used to graphically represent a three dimensional (3D) model on a two dimensional (2D) display screen. Also, the rendering method may perform pre-binning with respect to objects included in a frame, and thus all geometry processing results may not be stored in an external memory and use of the external memory may be reduced.

公开(公告)号：EP2434409B1

公开(公告)日：2020-07-15

申请号：EP11179435.0

申请日：2011-08-31

申请人： Samsung Electronics Co., Ltd.

发明人： Kwon, Kwon Taek

IPC分类号： G06F15/76

公开(公告)号：EP2778906A1

公开(公告)日：2014-09-17

申请号：EP14158460.7

申请日：2014-03-10

申请人： Samsung Electronics Co., Ltd.

发明人： Kwon, Kwon Taek ,  Woo, Sang Oak ,  Lee, Shi Hwa ,  Jung, Seok Yoon

IPC分类号： G06F9/38

CPC分类号： G06F9/3836 ,  G06F9/30043 ,  G06F9/3832 ,  G06F9/3842 ,  G06F9/3859

摘要： An apparatus and method for non-blocking execution of a static scheduled processor, the apparatus including a processor to process at least one operation using transferred input data, and an input buffer used to transfer the input data to the processor, and store a result of processing the at least one operation, wherein the processor may include at least one functional unit (FU) to execute the at least one operation, and the at least one FU may process the transferred input data using at least one of a regular latency operation and an irregular latency operation.

摘要翻译： 为非阻塞一个静态调度处理器的执行，该设备包括处理器使用传输的输入数据进行处理的至少一个操作，并INPUTBUFFER用于将输入数据传送到所述处理器，并存储结果的装置和方法 处理所述至少一个操作，worin处理器可以包括至少一个功能单元（FU），以执行所述至少一个操作，并且所述至少一个FU可以使用常规延迟操作的至少一个处理该传输的输入数据和 以不规则的延时操作。

公开(公告)号：EP2315180A3

公开(公告)日：2017-04-05

申请号：EP10178164.9

申请日：2010-09-22

申请人： Samsung Electronics Co., Ltd.

发明人： Woo, Sang Oak ,  Jung, Seok Yoon ,  Kwon, Kwon Taek

IPC分类号： G06T15/00

CPC分类号： G06T15/005 ,  G06T2210/12

摘要： A tile based rendering apparatus and method is provided. The rendering method may be used to graphically represent a three dimensional (3D) model on a two dimensional (2D) display screen. Also, the rendering method may perform pre-binning with respect to objects included in a frame, and thus all geometry processing results may not be stored in an external memory and use of the external memory may be reduced.

摘要翻译： 提供了一种基于瓦片的渲染装置和方法。 渲染方法可以用于在二维（2D）显示屏上图形地表示三维（3D）模型。 此外，渲染方法可以对于包括在帧中的对象执行预分类，因此所有几何处理结果可能不被存储在外部存储器中，并且可以减少外部存储器的使用。

公开(公告)号：EP2434409A1

公开(公告)日：2012-03-28

申请号：EP11179435.0

申请日：2011-08-31

申请人： Samsung Electronics Co., Ltd.

发明人： Kwon, Kwon Taek

IPC分类号： G06F15/76

摘要： A processor and an operating method are described. By diversifying an L1 memory being accessed, based on an execution mode of the processor, an operating performance of the processor may be enhanced. By disposing a local/stack section in a system dynamic random access memory (DRAM) located external to the processor, a size of a scratch pad memory may be reduced without deteriorating a performance. While a core of the processor is performing in a very long instruction word (VLIW) mode, the core may data-access a cache memory and thus, a bottleneck may not occur with respect to the scratch pad memory even though a memory access occurs with respect to the scratch pad memory by an external component.

摘要翻译： 描述处理器和操作方法。 通过使正在访问的L1存储器多样化，基于处理器的执行模式，可以提高处理器的操作性能。 通过将局部/堆叠部分设置在位于处理器外部的系统动态随机存取存储器（DRAM）中，可以减小暂存器存储器的尺寸，而不会降低性能。 虽然处理器的核心以非常长的指令字（VLIW）模式执行，但核心可以数据访问高速缓冲存储器，因此即使存储器访问发生在与暂存器存储器相关的情况下也可能不发生瓶颈 通过外部组件对于临时存储器的存储器。