SEMICONDUCTOR MEMORY DEVICE
    1.
    发明公开

    公开(公告)号:EP4415497A3

    公开(公告)日:2024-08-28

    申请号:EP23205348.8

    申请日:2023-10-23

    IPC分类号: H10B12/00 H01L29/786

    摘要: A semiconductor memory device, which may include a substrate, a lower conductive line on the substrate, an isolation insulating layer on the lower conductive line and including a channel trench, a channel structure inside the channel trench and including a first oxide semiconductor material, an interfacial conductive pattern between the lower conductive line and a lower surface of the channel structure, a gate dielectric layer that covers the channel structure within the channel trench, an upper conductive line on the gate dielectric layer within the channel trench, a conductive contact pattern on the channel structure, an interfacial oxide semiconductor pattern between the channel structure and the conductive contact pattern and including a second oxide semiconductor material, and a capacitor structure including a lower electrode connected to the conductive contact pattern.

    SEMICONDUCTOR MEMORY DEVICE
    2.
    发明公开

    公开(公告)号:EP4415497A2

    公开(公告)日:2024-08-14

    申请号:EP23205348.8

    申请日:2023-10-23

    IPC分类号: H10B12/00 H01L29/786

    摘要: A semiconductor memory device, which may include a substrate, a lower conductive line on the substrate, an isolation insulating layer on the lower conductive line and including a channel trench, a channel structure inside the channel trench and including a first oxide semiconductor material, an interfacial conductive pattern between the lower conductive line and a lower surface of the channel structure, a gate dielectric layer that covers the channel structure within the channel trench, an upper conductive line on the gate dielectric layer within the channel trench, a conductive contact pattern on the channel structure, an interfacial oxide semiconductor pattern between the channel structure and the conductive contact pattern and including a second oxide semiconductor material, and a capacitor structure including a lower electrode connected to the conductive contact pattern.