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公开(公告)号:EP3863058B1
公开(公告)日:2024-09-25
申请号:EP19869683.3
申请日:2019-04-01
IPC: H01L25/075 , H01L29/786 , H01L33/62 , H01L33/24
CPC classification number: H01L33/62 , H01L25/0753 , H01L29/7869 , H01L33/24
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2.
公开(公告)号:EP3651209B1
公开(公告)日:2024-09-04
申请号:EP19219861.2
申请日:2006-06-09
IPC: H01L27/12 , H01L29/786 , H01L29/66 , G02F1/1368
CPC classification number: G02F1/1368 , H01L29/7869 , H01L29/66969 , H01L27/1225
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公开(公告)号:EP4415497A3
公开(公告)日:2024-08-28
申请号:EP23205348.8
申请日:2023-10-23
Applicant: Samsung Electronics Co., Ltd.
Inventor: LEE, Wonsok , LEE, Juho , KIM, Seunghyun , JUNG, Wooje , CHO, Minhee
IPC: H10B12/00 , H01L29/786
CPC classification number: H10B12/05 , H01L29/7869 , H10B12/0335 , H10B12/315 , H01L29/78642
Abstract: A semiconductor memory device, which may include a substrate, a lower conductive line on the substrate, an isolation insulating layer on the lower conductive line and including a channel trench, a channel structure inside the channel trench and including a first oxide semiconductor material, an interfacial conductive pattern between the lower conductive line and a lower surface of the channel structure, a gate dielectric layer that covers the channel structure within the channel trench, an upper conductive line on the gate dielectric layer within the channel trench, a conductive contact pattern on the channel structure, an interfacial oxide semiconductor pattern between the channel structure and the conductive contact pattern and including a second oxide semiconductor material, and a capacitor structure including a lower electrode connected to the conductive contact pattern.
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公开(公告)号:EP4396816A1
公开(公告)日:2024-07-10
申请号:EP22865278.0
申请日:2022-08-04
Applicant: Sunrise Memory Corporation
Inventor: PETTI, Christopher J. , HARARI, Eli
CPC classification number: G11C11/223 , G11C11/2259 , H10B51/20 , H01L29/7869
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5.
公开(公告)号:EP4394887A1
公开(公告)日:2024-07-03
申请号:EP23217231.2
申请日:2023-12-15
Applicant: LG Display Co., Ltd.
Inventor: Seul, Hyeonjoo , Jung, Jinwon , Choi, Sungju , Park, Jaeyoon
IPC: H01L29/417 , H01L29/66 , H01L29/786 , H01L27/12
CPC classification number: H01L29/7869 , H01L29/78696 , H01L29/41733 , H01L29/66969 , H01L27/1225
Abstract: A thin film transistor including an active layer including a channel, a first connection portion and a second connection portion contacting opposite sides of the channel; and a gate electrode overlapping the channel of the active layer. Further, the active layer includes a first active layer; a second active layer on the first active layer in the first connection portion and the second connection portion of the active layer; and a third active layer contacting the first active layer in the channel and contacting the second active layer in the first connection portion and the second connection portion.
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公开(公告)号:EP4371152A1
公开(公告)日:2024-05-22
申请号:EP22841579.0
申请日:2022-07-11
Applicant: Zinite Corporation
Inventor: BARLAGE, Douglas W. , SHOUTE, Lhing Gem
IPC: H01L23/535 , H01L29/772
CPC classification number: H01L29/66969 , H01L29/7869 , H01L29/78696 , H01L29/45
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公开(公告)号:EP1984953B1
公开(公告)日:2018-12-12
申请号:EP07715131.4
申请日:2007-02-23
Applicant: Canon Kabushiki Kaisha
Inventor: HAYASHI, Ryo , ABE, Katsumi , SANO, Masafumi
CPC classification number: H01L29/7869 , H01L21/02422 , H01L21/02554 , H01L21/02565 , H01L21/02631 , H01L21/28202 , H01L29/4908 , H01L29/518 , H01L29/66969
Abstract: The thin-film transistor of the present invention has at least a semiconductor layer including: on a substrate, a source electrode, a drain electrode, and a channel region; a gate insulating film; and a gate electrode, wherein the semiconductor layer is an oxide semiconductor layer, and wherein the gate insulating film is amorphous silicon including at least O and N, and the gate insulating film has a distribution of an oxygen concentration in a thickness direction so that the oxygen concentration is high in the side of an interface with an oxide semiconductor layer and the oxygen concentration decreases toward the side of the gate electrode.
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公开(公告)号:EP3410490A2
公开(公告)日:2018-12-05
申请号:EP18173345.2
申请日:2018-05-18
Applicant: Mikuni Electron Corporation
Inventor: TANAKA, Sakae
CPC classification number: H01L27/3262 , H01L27/1225 , H01L27/1248 , H01L27/1288 , H01L27/3248 , H01L27/3258 , H01L29/42384 , H01L29/66969 , H01L29/78648 , H01L29/7869 , H01L51/5072 , H01L51/5092 , H01L51/5218 , H01L51/5271 , H01L51/56 , H01L2227/323 , H01L2251/303
Abstract: A display device includes a transistor includes an oxide semiconductor layer (112a), a first gate electrode (104a), a first insulating layer (106), and a transparent conductive layer (108a), and an organic EL element (130) includes a first electrode (146) being light-transmissive, and a second electrode (158), a light emitting layer (152), and an electron transfer layer (144). The first gate electrode including a region overlapping the oxide semiconductor layer, the first insulating layer provided between the first gate electrode and the oxide semiconductor layer, the transparent conductive layer provided between the first insulating layer and the oxide semiconductor layer, and at least including a region in contact with the oxide semiconductor layer, the first electrode including a region overlapping the second electrode, the light emitting layer and the electron transfer layer provided between the first electrode and the second electrode, the electron transfer layer provided between the first electrode and the light emitting layer, and the first electrode is continuous from the transparent conductive layer.
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公开(公告)号:EP2808893B1
公开(公告)日:2018-10-24
申请号:EP13196182.3
申请日:2013-12-09
Applicant: LG Display Co., Ltd.
Inventor: Seo, Hyun-Sik , Kim, Jong-Woo , Lee, Chung-Ho
IPC: H01L29/66 , H01L27/32 , G02F1/1362 , H01L27/12 , H01L29/786 , H01L29/45
CPC classification number: H01L27/3279 , G02F2001/13629 , H01L27/124 , H01L27/1244 , H01L29/45 , H01L29/66765 , H01L29/66969 , H01L29/78648 , H01L29/78669 , H01L29/78678 , H01L29/7869
Abstract: A thin film transistor (TFT) array substrate is disclosed. The TFT array substrate includes a gate line (6L), a first gate electrode (6E1) branched from the gate line (6L), a gate insulating film (102) formed over the substrate (101), an active layer (ACT) formed on the gate insulating film (102), a data line (DL) formed to comprise a plurality of metal layers including a first metal layer and a second metal layer formed of copper (Cu), a source electrode (SE) formed on the gate insulating film (102) to comprise the remaining metal layer excluding the second metal layer among the plurality of the metal layers, and a drain electrode (DE) formed on the gate insulating film (102) to comprise the remaining metal layer excluding the second metal layer among the plurality of the metal layers.
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公开(公告)号:EP2507823B1
公开(公告)日:2018-09-26
申请号:EP10834489.6
申请日:2010-11-15
Applicant: Semiconductor Energy Laboratory Co. Ltd.
Inventor: YAMAZAKI, Shunpei , SAKATA, Junichiro , OHARA, Hiroki
IPC: H01L29/786 , H01L29/66 , H01L29/78 , H01L21/20 , H01L21/324 , H01L21/28 , G02F1/1368 , H01L29/49
CPC classification number: H01L29/7831 , H01L21/28176 , H01L21/324 , H01L29/4966 , H01L29/66969 , H01L29/78642 , H01L29/7869
Abstract: A semiconductor device for high power application in which a novel semiconductor material having high mass productivity is provided. An oxide semiconductor film is formed, and then, first heat treatment is performed on the exposed oxide semiconductor film in order to reduce impurities such as moisture or hydrogen in the oxide semiconductor film. Next, in order to further reduce impurities such as moisture or hydrogen in the oxide semiconductor film, oxygen is added to the oxide semiconductor film by an ion implantation method, an ion doping method, or the like, and after that, second heat treatment is performed on the exposed oxide semiconductor film.
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