-
公开(公告)号:EP4395525A2
公开(公告)日:2024-07-03
申请号:EP23185777.2
申请日:2023-07-17
Applicant: Samsung Electronics Co., Ltd.
Inventor: KIM, Seyun , KANG, Jooheon , Yumin, KIM , PARK, Garam , SONG, Hyunjae , AHN, Dongho , YANG, Seungyeul , WOO, Myunghun , LEE, Jinwoo , HYUN, Seungdam
CPC classification number: H10N70/8833 , H10N70/24 , H10N70/8265 , H10N70/061 , H10N70/023 , H10B63/34 , H10B63/84 , H10N70/828
Abstract: Disclosed is a resistive memory device (CS) including a vertical stack of memory cells (MC), each memory cell comprising a gate electrode (140), a resistance change layer (124), a (semiconductor transistor) channel (132) between the gate electrode and the resistance change layer, an island structure (128) between and in contact with the resistance change layer and the channel, and a gate insulating layer (136) between the gate electrode and the channel. Preferably, the island structure includes SiN, GaN, or an oxide having a greater absolute value of oxide formation energy than the resistance change layer. A method of fabricating such memory cells is also disclosed.
-
公开(公告)号:EP4391761A1
公开(公告)日:2024-06-26
申请号:EP23187580.8
申请日:2023-07-25
Applicant: Samsung Electronics Co., Ltd.
Inventor: KIM, Kyunghun , KIM, Sunho , KIM, Seyun , KIM, Hyungyung , YANG, Seungyeul , YON, Gukhyon , LEE, Minhyun , CHOI, Seokhoon , HEO, Hoseok
IPC: H10B43/27 , H10B43/30 , H01L29/423 , H01L29/792
CPC classification number: H10B43/30 , H10B43/27 , H01L29/42324 , H01L29/7926
Abstract: A vertical NAND flash memory device may include a plurality of cell arrays (110). Each of the plurality of cell arrays may include a channel layer (129), a charge trap layer (125) on the channel layer, and a plurality of gate electrodes (121) on the charge trap layer. The charge trap layer may include silicon oxynitride comprising a metal. The metal may include at least one of Ga or In.
-
公开(公告)号:EP3965160A1
公开(公告)日:2022-03-09
申请号:EP21178809.6
申请日:2021-06-10
Applicant: Samsung Electronics Co., Ltd.
Inventor: KIM, Yumin , KIM, Seyun , KIM, Jinhong , MIZUSAKI, Soichiro , CHO, Youngjin
Abstract: The disclosed memory device (200) includes a protrusion portion (211) protruding from a first surface (210a) of an insulating structure (210) in a first direction (D1), a recording material layer (230) extending along a protruding surface (210b) of the protrusion portion and onto the first surface (210a), a channel layer (240) extending along a surface of the recording material layer, a gate insulating layer (250) on the channel layer, and a gate electrode (260) on the gate insulating layer at a location facing the protruding surface (210b). Preferably, a plurality of gate electrodes (260) are arranged along a second direction (D2), to realise a vertical NAND memory in which a plurality of memory cells (MC) are arrayed in a vertical direction.
-
公开(公告)号:EP4326029A3
公开(公告)日:2024-03-27
申请号:EP23169766.5
申请日:2023-04-25
Applicant: Samsung Electronics Co., Ltd.
Inventor: KIM, Seyun , KANG, Jooheon , KIM, Sunho , KIM, Yumin , PARK, Garam , SONG, Hyunjae , AHN, Dongho , YANG, Seungyeul , WOO, Myunghun , LEE, Jinwoo
Abstract: Provided area a variable resistance memory device and/or an electronic device including the same. The variable resistance memory device includes: a resistance change layer including a metal oxide having an oxygen deficient ratio greater than or equal to about 9%; a semiconductor layer on the resistance change layer; a gate insulating layer on the semiconductor layer; and a plurality of electrodes on the gate insulating layer to be apart from each other.
-
公开(公告)号:EP3961735A1
公开(公告)日:2022-03-02
申请号:EP21190578.1
申请日:2021-08-10
Applicant: Samsung Electronics Co., Ltd.
Inventor: KIM, Seyun , KIM, Doyoon , KIM, Yumin , KIM, Jinhong , MIZUSAKI, Soichiro , CHO, Youngjin
Abstract: The disclosed variable resistance memory device (100) includes first and second conductive elements (E1, E2) which are spaced apart from each other on a variable resistance layer (130) which comprises a first layer (11) and a second layer (12) on the first layer, wherein the first layer includes a ternary or higher metal oxide containing two or more metals having different valences. For example, the first layer includes hafnium aluminum oxide and the second layer includes silicon oxide. The first and second conductive elements, in response to an applied voltage, form a current path in a direction perpendicular to a direction in which the first layer and the second direction are stacked. The variable resistance memory device has a wide range of resistance variation due to the metal oxide in which oxygen vacancies are easily formed.
-
公开(公告)号:EP3852144A1
公开(公告)日:2021-07-21
申请号:EP21151132.4
申请日:2021-01-12
Applicant: Samsung Electronics Co., Ltd.
Inventor: CHO, Youngjin , YOON, Jungho , KIM, Seyun , KIM, Jinhong , MIZUSAKI, Soichiro
Abstract: A vertical nonvolatile memory device including a memory cell string (CS) using a resistance change material is disclosed. Each memory cell string of the nonvolatile memory device includes a semiconductor layer (522) extending in a first direction and having a first surface opposite a second surface, a plurality of gates (531) and a plurality of insulators (532) alternately arranged in the first direction and extending in a second direction perpendicular to the first direction, a gate insulating layer (521) extending in the first direction between the plurality of gates and the semiconductor layer and between the plurality of insulators and the semiconductor layer, and a dielectric film (523) extending in the first direction on the surface of the semiconductor layer and having a plurality of movable oxygen vacancies distributed therein.
-
公开(公告)号:EP4326029A2
公开(公告)日:2024-02-21
申请号:EP23169766.5
申请日:2023-04-25
Applicant: Samsung Electronics Co., Ltd.
Inventor: KIM, Seyun , KANG, Jooheon , KIM, Sunho , KIM, Yumin , PARK, Garam , SONG, Hyunjae , AHN, Dongho , YANG, Seungyeul , WOO, Myunghun , LEE, Jinwoo
Abstract: Provided area a variable resistance memory device and/or an electronic device including the same. The variable resistance memory device includes: a resistance change layer including a metal oxide having an oxygen deficient ratio greater than or equal to about 9%; a semiconductor layer on the resistance change layer; a gate insulating layer on the semiconductor layer; and a plurality of electrodes on the gate insulating layer to be apart from each other.
-
公开(公告)号:EP3321939B1
公开(公告)日:2019-08-21
申请号:EP17201682.6
申请日:2017-11-14
Applicant: Samsung Electronics Co., Ltd.
Inventor: BAE, Minjong , KIM, Jinhong , KIM, Hajin , KOH, Haengdeog , KIM, Doyoon , KIM, Seyun , MIZUSAKI, Soichiro , SOHN, Hiesang , LEE, Changsoo
-
公开(公告)号:EP4325502A1
公开(公告)日:2024-02-21
申请号:EP23157812.1
申请日:2023-02-21
Applicant: Samsung Electronics Co., Ltd.
Inventor: KIM, Yumin , KANG, Jooheon , KIM, Sunho , KIM, Seyun , GARAM, Park , SONG, Hyunjae , AHN, Dongho , YANG, Seungyeul , WOO, Myunghun , LEE, Jinwoo
Abstract: Provided are a nonvolatile memory device and an operating method thereof. The nonvolatile memory device may include a conductive pillar, a resistance change layer surrounding a side surface of the conductive pillar, a semiconductor layer surrounding a side surface of the resistance change layer, a gate insulating layer surrounding a side surface of the semiconductor layer, and a plurality of insulating patterns and a plurality of gate electrodes alternately arranged along a surface of the gate insulating layer. The plurality of insulating patterns and the plurality of gate electrodes may surround a side surface of the gate insulating layer.
-
公开(公告)号:EP3944326A1
公开(公告)日:2022-01-26
申请号:EP21180142.8
申请日:2021-06-17
Applicant: Samsung Electronics Co., Ltd.
Inventor: KIM, Jinhong , KIM, Seyun , CHO, Youngjin
Abstract: A vertical nonvolatile memory device including memory cell strings using a resistance change material is provided. Each of the memory cell strings of the nonvolatile memory device includes a semiconductor layer (522) extending in a first direction; a plurality of gates (531) and a plurality of insulators (532) alternately arranged in the first direction; a gate insulating layer (521) extending in the first direction between the plurality of gates and the semiconductor layer and between the plurality of insulators and the semiconductor layer; and a resistance change layer (523) extending in the first direction on a surface of the semiconductor layer. The resistance change layer includes a metal-semiconductor oxide including a mixture of a semiconductor material of the semiconductor layer and a transition metal oxide.
-
-
-
-
-
-
-
-
-