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公开(公告)号：EP4326029A2
公开(公告)日：2024-02-21
申请号：EP23169766.5
申请日：2023-04-25
发明人： KIM, Seyun , KANG, Jooheon , KIM, Sunho , KIM, Yumin , PARK, Garam , SONG, Hyunjae , AHN, Dongho , YANG, Seungyeul , WOO, Myunghun , LEE, Jinwoo
摘要： Provided area a variable resistance memory device and/or an electronic device including the same. The variable resistance memory device includes: a resistance change layer including a metal oxide having an oxygen deficient ratio greater than or equal to about 9%; a semiconductor layer on the resistance change layer; a gate insulating layer on the semiconductor layer; and a plurality of electrodes on the gate insulating layer to be apart from each other.
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公开(公告)号：EP4395525A2
公开(公告)日：2024-07-03
申请号：EP23185777.2
申请日：2023-07-17
发明人： KIM, Seyun , KANG, Jooheon , Yumin, KIM , PARK, Garam , SONG, Hyunjae , AHN, Dongho , YANG, Seungyeul , WOO, Myunghun , LEE, Jinwoo , HYUN, Seungdam
CPC分类号： H10N70/8833 , H10N70/24 , H10N70/8265 , H10N70/061 , H10N70/023 , H10B63/34 , H10B63/84 , H10N70/828
摘要： Disclosed is a resistive memory device (CS) including a vertical stack of memory cells (MC), each memory cell comprising a gate electrode (140), a resistance change layer (124), a (semiconductor transistor) channel (132) between the gate electrode and the resistance change layer, an island structure (128) between and in contact with the resistance change layer and the channel, and a gate insulating layer (136) between the gate electrode and the channel. Preferably, the island structure includes SiN, GaN, or an oxide having a greater absolute value of oxide formation energy than the resistance change layer. A method of fabricating such memory cells is also disclosed.
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公开(公告)号：EP4395525A3
公开(公告)日：2024-09-18
申请号：EP23185777.2
申请日：2023-07-17
发明人： KIM, Seyun , KANG, Jooheon , Yumin, KIM , PARK, Garam , SONG, Hyunjae , AHN, Dongho , YANG, Seungyeul , WOO, Myunghun , LEE, Jinwoo , HYUN, Seungdam
CPC分类号： H10N70/8833 , H10N70/24 , H10N70/8265 , H10N70/061 , H10N70/023 , H10B63/34 , H10B63/84 , H10N70/828 , H10B43/35 , H10B43/10 , G11C16/0483 , H10B43/27
摘要： Disclosed is a resistive memory device (CS) including a vertical stack of memory cells (MC), each memory cell comprising a gate electrode (140), a resistance change layer (124), a (semiconductor transistor) channel (132) between the gate electrode and the resistance change layer, an island structure (128) between and in contact with the resistance change layer and the channel, and a gate insulating layer (136) between the gate electrode and the channel. Preferably, the island structure includes SiN, GaN, or an oxide having a greater absolute value of oxide formation energy than the resistance change layer. A method of fabricating such memory cells is also disclosed.
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公开(公告)号：EP4326029A3
公开(公告)日：2024-03-27
申请号：EP23169766.5
申请日：2023-04-25
发明人： KIM, Seyun , KANG, Jooheon , KIM, Sunho , KIM, Yumin , PARK, Garam , SONG, Hyunjae , AHN, Dongho , YANG, Seungyeul , WOO, Myunghun , LEE, Jinwoo
摘要： Provided area a variable resistance memory device and/or an electronic device including the same. The variable resistance memory device includes: a resistance change layer including a metal oxide having an oxygen deficient ratio greater than or equal to about 9%; a semiconductor layer on the resistance change layer; a gate insulating layer on the semiconductor layer; and a plurality of electrodes on the gate insulating layer to be apart from each other.
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公开(公告)号：EP4325502A1
公开(公告)日：2024-02-21
申请号：EP23157812.1
申请日：2023-02-21
发明人： KIM, Yumin , KANG, Jooheon , KIM, Sunho , KIM, Seyun , GARAM, Park , SONG, Hyunjae , AHN, Dongho , YANG, Seungyeul , WOO, Myunghun , LEE, Jinwoo
摘要： Provided are a nonvolatile memory device and an operating method thereof. The nonvolatile memory device may include a conductive pillar, a resistance change layer surrounding a side surface of the conductive pillar, a semiconductor layer surrounding a side surface of the resistance change layer, a gate insulating layer surrounding a side surface of the semiconductor layer, and a plurality of insulating patterns and a plurality of gate electrodes alternately arranged along a surface of the gate insulating layer. The plurality of insulating patterns and the plurality of gate electrodes may surround a side surface of the gate insulating layer.
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