SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME

    公开(公告)号:EP4243063A3

    公开(公告)日:2023-11-15

    申请号:EP22213564.2

    申请日:2022-12-14

    摘要: Disclosed are semiconductor devices and fabrication methods thereof. The semiconductor device includes a substrate including first (NR1) and second (PR1) regions, a device isolation pattern (ST) in the substrate, a lower separation dielectric pattern (BDI) on the first region of the substrate, first channel patterns (CH1) on the lower separation dielectric pattern, a first gate electrode (GE1) on the first channel patterns and including a first gate part between the lower separation dielectric pattern and a lowermost first channel pattern, and first source/drain patterns (SD1) on opposite sides of the first gate electrode and in contact with lateral surfaces of the first channel patterns. A bottom surface of the lower separation dielectric pattern is at a level higher than or equal to that of a bottom surface of the device isolation pattern. A top end of the lower separation dielectric pattern is at a level higher than that of a bottom surface of the first gate part.

    SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME

    公开(公告)号:EP4243063A2

    公开(公告)日:2023-09-13

    申请号:EP22213564.2

    申请日:2022-12-14

    摘要: Disclosed are semiconductor devices and fabrication methods thereof. The semiconductor device includes a substrate including first (NR1) and second (PR1) regions, a device isolation pattern (ST) in the substrate, a lower separation dielectric pattern (BDI) on the first region of the substrate, first channel patterns (CH1) on the lower separation dielectric pattern, a first gate electrode (GE1) on the first channel patterns and including a first gate part between the lower separation dielectric pattern and a lowermost first channel pattern, and first source/drain patterns (SD1) on opposite sides of the first gate electrode and in contact with lateral surfaces of the first channel patterns. A bottom surface of the lower separation dielectric pattern is at a level higher than or equal to that of a bottom surface of the device isolation pattern. A top end of the lower separation dielectric pattern is at a level higher than that of a bottom surface of the first gate part.