公开(公告)号：EP4434088A1

公开(公告)日：2024-09-25

申请号：EP22808976.9

申请日：2022-10-13

申请人： International Business Machines Corporation

发明人： XIE, Ruilong ,  SIEG, Stuart ,  GHOSH, Somnath ,  CHOI, Kisik ,  PETRARCA, Kevin, Shawn

IPC分类号： H01L23/535 ,  H01L21/768 ,  H01L29/78 ,  H01L23/528

CPC分类号： H01L23/535 ,  H01L23/5286 ,  H01L21/76897 ,  H01L21/76895 ,  H01L29/78696 ,  H01L29/42392 ,  H01L29/66439 ,  H01L21/84 ,  H01L27/1203 ,  H01L21/823475 ,  H01L27/088 ,  H01L21/823418 ,  B82Y10/00 ,  H01L29/0673 ,  H01L29/775 ,  H01L29/0847 ,  H01L29/1079 ,  H01L21/76898

公开(公告)号：EP4404252A3

公开(公告)日：2024-09-25

申请号：EP23217582.8

申请日：2023-12-18

申请人： Samsung Electronics Co., Ltd.

发明人： BAEK, Jaejik ,  YUN, Seungchan ,  SEO, Kang-ill

IPC分类号： H01L21/822 ,  H01L21/8234 ,  H01L27/06 ,  H01L27/088 ,  H01L29/06 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC分类号： H01L27/088 ,  H01L27/0688 ,  H01L21/8221 ,  H01L21/823462 ,  H01L21/82345 ,  H01L21/823481 ,  H01L29/775 ,  H01L29/0673 ,  H01L29/66439 ,  H01L29/78696 ,  H01L29/42392

摘要： Provided is a three-dimensionally-stacked field-effect transistor, 3DSFET, device including a plurality of 3DSFET structures on a single substrate, wherein each of the 3DSFET structures includes: a 1st channel structure surrounded by a 1st gate structure; and a 2nd channel structure surrounded by a 2nd gate structure, the 2nd channel structure provided on the 1st channel structure, and wherein, in at least one of the 3DSFETs, the 1st gate structure is isolated from the 2nd gate structure through a barrier layer including a dielectric material comprising tantalum.

公开(公告)号：EP4425540A1

公开(公告)日：2024-09-04

申请号：EP23215097.9

申请日：2023-12-07

申请人： INTEL Corporation

发明人： XU, Guowei ,  CHU, Tao ,  HUANG, Chiao-Ti ,  CHAO, Robin ,  TOWNER, David ,  ACTON, Orb ,  SAADAT, Omair ,  ZHANG, Feng ,  CRUM, Dax M. ,  ZHANG, Yang ,  GUHA, Biswajeet ,  GOLONZKA, Oleg ,  MURTHY, Anand S.

IPC分类号： H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC分类号： H01L27/092 ,  H01L21/823842 ,  H01L29/775 ,  H01L29/0673 ,  H01L29/66439 ,  H01L29/78696 ,  H01L29/42392

摘要： A metal gate fabrication method for nanoribbon-based transistors and associated transistor arrangements, IC structures, and devices are disclosed. An example IC structure fabricated using metal gate fabrication method described herein may include a first stack of N-type nanoribbons, a second stack of P-type nanoribbons, a first gate region enclosing portions of the nanoribbons of the first stack and including an NWF material between adjacent nanoribbons of the first stack, and a second gate region enclosing portions of the nanoribbons of the second stack and including a PWF material between adjacent nanoribbons of the second stack, where the second gate region includes the PWF material at sidewalls of the nanoribbons of the second stack and further includes the NWF material so that the PWF material is between the sidewalls of the nanoribbons of the second stack and the NWF material.

公开(公告)号：EP4391039A1

公开(公告)日：2024-06-26

申请号：EP22215085.6

申请日：2022-12-20

申请人： Imec VZW ,  Katholieke Universiteit Leuven KU Leuven Research & Development

发明人： CHAN, Boon Teik ,  LIU, Hsiao-Hsuan ,  SALAHUDDIN, Shairfe Muhammad

IPC分类号： H01L21/822 ,  H01L21/8238 ,  H01L27/06 ,  H01L27/092 ,  H01L29/06 ,  H01L29/775

CPC分类号： H01L27/0688 ,  H01L21/8221 ,  H01L29/775 ,  H01L29/0673 ,  H01L27/092 ,  H01L21/823878 ,  H01L21/823871 ,  B82Y10/00 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/165 ,  H01L29/78696

摘要： The disclosure relates to a method for forming a semiconductor device, comprising:
forming a first bottom and top channel structures, and second bottom and top channel structures, and a sacrificial gate extending across the channel structures;
forming an opening in the sacrificial gate, over the first top channel structure and forming a cut through the first top channel structure;
forming a dielectric plug in the cut and the opening;
removing the sacrificial gate and subsequently forming an RMG structure comprising a first gate stack on the first bottom channel structure and a second gate stack on the second bottom and top channel structures,;
forming pairs of S/D structures on the first bottom channel structure, the second bottom channel structure, and the second top channel structure;
forming S/D contacts on the S/D structures;
forming a trench for a cross-couple contact by etching a dielectric gate capping layer and a dielectric contact capping layer, the trench extending from the second gate stack, over the dielectric plug, to a first S/D contact on a first S/D structure of the pair of S/D structures on the first bottom channel structure; and
forming the cross-couple contact in the trench, the contact interconnecting the second gate stack and the first S/D contact.

公开(公告)号：EP3859769B1

公开(公告)日：2024-06-26

申请号：EP21153243.7

申请日：2021-01-25

IPC分类号： H01L21/3065 ,  H01L29/78 ,  H01L29/06 ,  B82Y10/00 ,  H01L29/161 ,  H01L29/66 ,  H01L29/739 ,  H01L29/775 ,  H01L29/786

CPC分类号： H01L21/3065 ,  H01L29/775 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/161 ,  H01L29/7391 ,  H01L29/66439 ,  H01L29/66356 ,  B82Y10/00 ,  H01L29/78684

公开(公告)号：EP4386851A1

公开(公告)日：2024-06-19

申请号：EP23200754.2

申请日：2023-09-29

申请人： INTEL Corporation

发明人： JUN, Hwichan

IPC分类号： H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/10 ,  H01L29/161

CPC分类号： H01L29/0847 ,  H01L29/0673 ,  H01L29/41725 ,  H01L29/161 ,  B82Y10/00 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/1079 ,  H01L29/42392 ,  H01L29/66545 ,  H01L21/28518

摘要： Techniques are provided herein to form semiconductor devices having one or more epitaxial source or drain regions wrapped by a conductive contact to form an improved ohmic contact. A first semiconductor device includes a first semiconductor region extending between a first source or drain region and a second source or drain region, and a second semiconductor device includes a second semiconductor region extending between the first source or drain region and a third source or drain region. The first and second semiconductor devices include a subfin region adjacent to a dielectric layer. A conductive layer extends around the first source or drain region such that the conductive layer at least contacts the sidewalls of the first source or drain region and both upper and lower surfaces of the source or drain region. A dielectric layer is also present between the conductive contact and the subfin region.

公开(公告)号：EP4383341A2

公开(公告)日：2024-06-12

申请号：EP23192937.3

申请日：2023-08-23

申请人： Samsung Electronics Co., Ltd.

发明人： SHIN, Dong Suk ,  KIM, Jung Taek ,  YU, Hyun-Kwan ,  KIM, Seok Hoon ,  PARK, Pan Kwi ,  JEONG, Seo Jin ,  CHO, Nam Kyu

IPC分类号： H01L29/06 ,  H01L29/08 ,  H01L29/161 ,  H01L29/165 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/201 ,  B82Y10/00 ,  H01L29/78 ,  H01L27/088

CPC分类号： B82Y10/00 ,  H01L29/0673 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/41766 ,  H01L29/7848 ,  H01L29/42392 ,  H01L29/201 ,  H01L27/088

摘要： There is provided a semiconductor device, preferably a nanosheet field-effect transistor, capable of improving performance and reliability of an element. The semiconductor device includes an active pattern (NS1) extending in a first direction, (D1) and a plurality of gate structures (INT_GS1) spaced apart from each other in the first direction on the active pattern. Each gate structure comprises a gate electrode (120) extending in a second direction and a gate spacer (GS1, 140) on a sidewall of the gate electrode and a source/drain pattern (150, 151, 152) disposed between adjacent gate structures. The source/drain structure comprises a semiconductor liner layer (151) and a semiconductor filling layer (152) on the semiconductor liner layer, wherein the semiconductor liner layer and the semiconductor filling layer are formed of silicon-germanium. The semiconductor filling layer comprises an upper portion (152UP) protruding in a third direction beyond an upper surface of the active pattern (NS1). A maximum width of the upper portion of the semiconductor filling layer in the first direction is greater than a width of the semiconductor filling layer in the first direction at the vertical position of the upper surface of the active pattern (NS1). Furthermore, in a plan view (Fig. 5), the inner surface of the semiconductor liner layer comprises a concave region.

公开(公告)号：EP4354510A1

公开(公告)日：2024-04-17

申请号：EP23202918.1

申请日：2023-10-11

申请人： Samsung Electronics Co., Ltd.

发明人： YOU, Junggun ,  PARK, Junki ,  KIM, Sunghwan ,  KIM, Wandon ,  SUNG, Sughyun ,  LEE, Hyunbae

IPC分类号： H01L29/40 ,  H01L29/06 ,  H01L21/285 ,  H01L21/336 ,  H01L29/417 ,  H01L29/423 ,  H01L29/775 ,  H01L29/78 ,  B82Y10/00

CPC分类号： B82Y10/00 ,  H01L29/42392 ,  H01L29/7848 ,  H01L29/66545 ,  H01L29/66439 ,  H01L29/0673 ,  H01L29/775 ,  H01L29/41766 ,  H01L21/28518 ,  H01L29/785 ,  H01L29/401 ,  H01L29/165 ,  H01L29/78696 ,  H01L23/485

摘要： A semiconductor device includes an active region (105) on a substrate (101), a plurality of channel layers (141-143) spaced apart from each other, a gate structure (160) on the substrate (101), a source/drain region (150) on at least one side of the gate structure (160), and a contact plug (180) connected to the source/drain region (150). The contact plug (180) includes a metal-semiconductor compound layer (182) and a barrier layer (184) on the metal-semiconductor compound layer (182). The barrier layer (184) includes a first inclined surface (184_1) and a second inclined surface (184_2) positioned where the metal-semiconductor compound layer (182) and the barrier layer (184) directly contact each other. The barrier layer (184) includes first and second ends (184e1, 184e2) protruding towards the gate structure (160). The first and second ends (184e1, 184e2) are positioned at a level higher than an upper surface of an uppermost channel layer (143). An uppermost portion of the metal-semiconductor compound layer (182) is positioned at a level higher than an upper surface of the source/drain region (150).

公开(公告)号：EP4202552B1

公开(公告)日：2024-04-17

申请号：EP21217706.7

申请日：2021-12-24

IPC分类号： G03F7/20 ,  G03F9/00 ,  H01L21/66 ,  H01L23/544 ,  H01L29/423

CPC分类号： G03F7/70616 ,  G03F7/70683 ,  G03F7/70633 ,  H01L22/34 ,  G03F9/7084 ,  G03F9/7088 ,  B82Y10/00 ,  H01L29/0673 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/41725 ,  H01L29/78642

公开(公告)号：EP3141523B1

公开(公告)日：2018-11-21

申请号：EP16188135.4

申请日：2016-09-09

申请人： Samsung Electronics Co., Ltd.

发明人： OH, Yeongtek ,  KWON, Hyeokshin ,  SUH, Hwansoo ,  JEON, Insu

IPC分类号： B82Y10/00 ,  B82Y40/00 ,  H01L29/66 ,  H01L29/775 ,  H01L29/06 ,  H01L29/16 ,  H01L21/02

CPC分类号： H01L29/0673 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/02425 ,  H01L21/02444 ,  H01L21/02458 ,  H01L21/02488 ,  H01L21/02499 ,  H01L21/02532 ,  H01L21/0254 ,  H01L21/02601 ,  H01L21/02603 ,  H01L21/02631 ,  H01L21/02639 ,  H01L29/16 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78 ,  H01L29/861

摘要： Provided are methods of forming nanostructures, methods of manufacturing semiconductor devices using the same, and semiconductor devices including nanostructures. A method of forming at least one nanostructure may include forming an insulating layer (N11) and forming at least one nanostructure (NW11) on the insulating layer. The insulating layer (N11) has a crystal structure and is a two-dimensional (2D) material, like hexagonal boron nitride (h-BN). The insulating layer may be formed on a catalyst metal layer (M11). The nanostructures may include at least one of silicon (Si), germanium (Ge), and SiGe. The nanostructure may include at least one nanowire and may be formed directly on the 2D insulating layer by evaporation. Devices may be formed that comprise a plurality of nanowires (NW11) in a network structure.