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公开(公告)号：EP4322164A1
公开(公告)日：2024-02-14
申请号：EP23160217.8
申请日：2023-03-06
发明人： LEE, Cheonan , SONG, Kiwhan , CHOO, Gyosoo , SUNG, Sukkang
摘要： The present disclosure provides serial-gate transistors and nonvolatile memory devices including serial-gate transistors. In some embodiments, a nonvolatile memory device includes a plurality of memory blocks, a plurality of pass transistor blocks, and a plurality of gates sequentially arranged in a horizontal direction in a gate region above a semiconductor substrate. Each of the plurality of pass transistor blocks includes a plurality of serial-gate transistors configured to transfer a plurality of driving signals to a corresponding memory block of the plurality of memory blocks. Each of the plurality of serial-gate transistors includes a first source-drain region, a gate region, and a second source-drain region that are sequentially arranged in a horizontal direction at a semiconductor substrate. The plurality of gates are electrically decoupled from each other. A plurality of block selection signals respectively applied to the plurality of gates are controlled independently of each other.
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公开(公告)号：EP4439667A1
公开(公告)日：2024-10-02
申请号：EP23220533.6
申请日：2023-12-28
发明人： SEO, Jungmin , SUNG, Sukkang , LEE, Cheonan , LEE, Sangeun , LEE, Chanho
IPC分类号： H01L27/02 , H01L29/06 , H01L29/861
摘要： A semiconductor device according to an embodiment of the present inventive concept comprises: a first power supply pad (201) configured to receive a first power supply voltage (VDD); a second power supply pad (202) configured to receive a second power supply voltage (VSS), the second power supply voltage (VSS) having a level lower than a level of the first power supply voltage (VDD); a signal pad (203) configured to exchange a signal; and a first electrostatic discharge (ESD) diode comprising a first impurity region (310) doped with impurities of a first conductivity type and connected to the first power supply pad (201), and a second impurity region (320) doped with impurities of a second conductivity type different from the first conductivity type and connected to the signal pad (203), wherein a lower surface of at least one of the first impurity region (310) and the second impurity region (320) has an uneven structure.
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3.发明公开
公开(公告)号：EP4432804A1
公开(公告)日：2024-09-18
申请号：EP23211159.1
申请日：2023-11-21
发明人： LEE, Ahreum , YANG, Woosung , GU, Jimo , SUNG, Sukkang
CPC分类号： H10B41/10 , H10B41/27 , H10B41/50 , H10B43/10 , H10B43/27 , H10B43/50 , H01L28/40 , H01L28/87
摘要： Disclosed are semiconductor devices which may include a substrate having first and second regions, a stack structure including electrode patterns and dielectric patterns, channels vertically penetrating the stack structure on the first region, a planarized dielectric layer covering the stack structure, and wiring patterns on the planarized dielectric layer. The dielectric pattern includes a first dielectric pattern on the first region, and a second dielectric pattern on the second region. The second dielectric pattern includes a first sub-dielectric pattern and a second sub-dielectric pattern. A dielectric constant of the first sub-dielectric patterns is greater than that of the first dielectric patterns and that of the second sub-dielectric patterns.
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公开(公告)号：EP4383981A1
公开(公告)日：2024-06-12
申请号：EP23211181.5
申请日：2023-11-21
发明人： KIM, Jaeho , YANG, Woosung , KWON, Joonyoung , KIM, Jiyoung , SUNG, Sukkang
摘要： A semiconductor device includes a first substrate structure (S1) including a substrate (201), circuit elements (220) on the substrate (201), a first interconnection structure (270, 280) on the circuit elements (220), and first metal bonding layers (298) on the first interconnection structure (270, 280); and a second substrate structure (S2) connected to the first substrate structure (S 1), and the second substrate structure (S2) includes: a plating layer (101); gate electrodes (130) stacked and spaced apart from each other in a first direction below the plating layer (101); channel structures (CH) penetrating through the gate electrodes (130) and extending in the first direction; a separation region (MS) penetrating through the gate electrodes (130) and extending in a second direction (X); a second interconnection structure (150, 155, 170, 180) below the gate electrodes (130) and the channel structures (CH); second metal bonding layers (198) below the second interconnection structure (150, 155, 170, 180) and connected to the first metal bonding layers (298); and dummy pattern layers (160) between the second metal bonding layers (198), extending in the second direction (X), and including an insulating material.
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公开(公告)号：EP4398694A1
公开(公告)日：2024-07-10
申请号：EP23191539.8
申请日：2023-08-15
发明人： KIM, Jiwon , LEE, Ahreum , KWON, Joonyoung , KIM, Dohyung , KIM, Junhyoung , SUNG, Sukkang
摘要： A semiconductor device includes a cell region (1) in which a channel structure (CH) is disposed and memory cells arranged in three dimensions are disposed, a cell contact region (2) in which a cell contact plug (340) is disposed, a common source line contact region (3) in which a common source line contact plug (380) is disposed, an input and output contact region (5) in which an input and output contact plug (203, 303, 304) is disposed, a word line cut region (4) configured to separate word lines of the cell region from word lines of a neighboring cell region, a common source line layer (320) configured to connect the channel structure and the common source line contact plug, and an input and output pad (17) connected to the input and output contact plug. The common source line layer and the input and output pad are disposed at the same vertical level.
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公开(公告)号：EP4387409A1
公开(公告)日：2024-06-19
申请号：EP23215568.9
申请日：2023-12-11
发明人： KIM, Jiwon , KIM, Jiyoung , YANG, Woosung , SUNG, Sukkang
摘要： A semiconductor device including a first semiconductor structure overlapping a second semiconductor structure, the second semiconductor structure having first and second regions (R1, R2) and including a plate layer (101); gate electrodes (130) spaced apart from each other in a first direction (Z); channel structures (CH; CHe) passing through the gate electrodes (130); gate separation regions (MS, MS2a, MS2b) extending in a second direction (X); first and second upper isolation regions (US) dividing an upper gate electrode (130U) into first, second and third sub-gate electrodes (SG_1, SG_2, SG_3) between adjacent gate separation regions (MS1, MS2a, MS2b); and contact plugs (170) extending in the first direction (Z), each of the first and second upper isolation regions (US) has a region extending in a third direction, and the first sub-gate electrode (SG_1) has a first pad region having a first width (W1) and a second pad region having a second width (W2) narrower than the first width (W1) in a fourth direction (Y), and the first sub-gate electrode (SG_1) is connected to one of the contact plugs (170).
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7.发明公开
公开(公告)号：EP4369882A1
公开(公告)日：2024-05-15
申请号：EP23199237.1
申请日：2023-09-22
发明人： KIM, Jiwon , KIM, Jiyoung , YANG, Woosung , KIM, Dohyung , SUNG, Sukkang
摘要： Disclosed are 3D semiconductor memory devices and electronic systems including the same. The 3D semiconductor memory device comprises a first substrate, a peripheral circuit structure on the first substrate, and a cell array structure on the peripheral circuit structure. The cell array structure includes a second substrate, a stack structure between the second substrate and the peripheral circuit structure and including interlayer dielectric layers and conductive patterns that are stacked alternately with the interlayer dielectric layers, vertical channel structures that include respective portions the stack structure and include vertical semiconductor patterns, respectively, and connection vias that include respective portions the second substrate and are connected to respective top surfaces of the vertical semiconductor patterns.
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公开(公告)号：EP4333060A1
公开(公告)日：2024-03-06
申请号：EP23194734.2
申请日：2023-08-31
发明人： KWON, Joonyoung , JEONG, Dawoon , KIM, Jiyoung , SUNG, Sukkang , YANG, Woosung
摘要： A semiconductor device includes a first conductive plate structure and a second conductive plate structure, arranged at a same vertical level on a semiconductor chip and horizontally spaced apart from each other on the semiconductor chip, a first structure on the first conductive plate structure and including first separation structures and first memory blocks, and a second structure on the second conductive plate structure and including second separation structures and second memory blocks. The first memory blocks are spaced apart from each other by the first separation structures, and extend in parallel to each other in a first horizontal direction. The second memory blocks are spaced apart from each other by the second separation structures, and extend in parallel to each other in a second horizontal direction. The first and second horizontal directions are parallel to an upper surface of the first conductive plate structure, and are perpendicular to each other.
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公开(公告)号：EP4301108A1
公开(公告)日：2024-01-03
申请号：EP23166859.1
申请日：2023-04-05
发明人： KIM, Jiwon , KIM, Dohyung , KIM, Jiyoung , SUNG, Sukkang
摘要： An integrated circuit device includes a semiconductor substrate, and a common source structure on the substrate. A vertical stack of memory cell gate electrodes is provided, which extends between the common source structure and the substrate. The vertical stack of memory cell gate electrodes includes a first erase control gate electrode, and a plurality of word lines extending between the first erase control gate electrode and the substrate. At least one channel structure is provided, which vertically penetrates through the vertical stack of memory cell gate electrodes. A source protrusion pattern is provided, which is electrically connected to the common source structure. The source protrusion pattern extends sufficiently through the vertical stack of memory cell gate electrodes that a portion of the source protrusion pattern extends opposite a sidewall of the first erase control gate electrode.
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公开(公告)号：EP4391050A1
公开(公告)日：2024-06-26
申请号：EP23192801.1
申请日：2023-08-22
发明人： KIM, Junhyoung , KIM, Jiwon , LEE, Minyong , KIM, Dohyung , SUNG, Sukkang
IPC分类号： H01L25/065 , H01L23/485 , H10B43/00 , H01L25/18
CPC分类号： H01L25/0657 , H01L25/18 , H01L24/06 , H01L2225/0656220130101 , H01L2225/0652720130101 , H01L2225/0656520130101 , H01L2225/0654120130101 , H01L2225/065120130101 , H01L24/20 , H10B43/00 , H01L24/08 , H01L24/05
摘要： The inventive concept provides a chip stack structure including a first semiconductor chip and a second semiconductor chip bonded to each other, and a semiconductor package including a plurality of chip stack structures stacked in a vertical direction. In each chip stack structure, a redistribution layer between pads of the first semiconductor chip and pads of the second semiconductor chip is present.
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