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    Memory cards including a standard security function
    6.
    发明公开
    Memory cards including a standard security function 审中-公开
    Speicherkarten mit Standardsicherheitsfunktion

    公开(公告)号：EP2256669A2

    公开(公告)日：2010-12-01

    申请号：EP10009241.0

    申请日：2004-03-11

    申请人： Sandisk Corporation

    发明人： Harari, Eliyahou ,  Cedar, Yoram ,  Brewer, Wesley G. ,  Yosi, Pinto ,  Reuven, Elhamias ,  Holtzman, Micky

    IPC分类号： G06K19/07 ,  G06K19/077

    CPC分类号： G06K19/07 ,  G06K19/0719 ,  G06K19/077 ,  G06K19/07732 ,  G06K19/07733 ,  G06K19/07743

    摘要： A memory system, comprising: a re-writable non-volatile memory; an external set of electrical contacts; and a controller connected to the re-writable non-volatile memory and the external contacts, the controller including: host interface circuitry connected to the external contacts; a first plurality of lines connected to the host interface circuitry for use when the memory system is operating according to a first protocol; and a second plurality of lines connected to the host interface circuitry for use when the memory system is operating according to a second protocol, wherein the host interface circuitry has a switching circuit connected with at least some of the first and second plurality of lines to make anyone of a plurality of connections in response to a command received through the external set of electrical contacts, the plurality of connections including connecting said at least some of the first plurality of lines to specified ones of the external contacts while maintaining the second plurality of lines disconnected therefrom and connecting said at least some of the second plurality of lines to said specified ones of the external contacts while maintaining the first plurality of lines disconnected therefrom.

    摘要翻译： 一种存储器系统，包括：可重写的非易失性存储器; 外部电气触点组; 以及连接到可重写非易失性存储器和外部触点的控制器，所述控制器包括：连接到所述外部触点的主机接口电路; 连接到所述主机接口电路的第一组多条线路，用于当所述存储器系统根据第一协议操作时使用; 以及连接到所述主机接口电路的第二多个线路，用于当所述存储器系统根据第二协议操作时使用，其中所述主机接口电路具有与所述第一和第二多个线路中的至少一些连接的切换电路，以使 响应于通过外部电触点接收的命令，多个连接中的任何一个连接，所述多个连接包括将第一多个线中的至少一些连接到指定的外部触点，同时保持第二多个线 从而断开连接，并且将所述第二多个线中的至少一些连接到所述指定的外部触点，同时保持所述第一多个线与其断开连接。

    Steering gate and bit line segmentation in non-volatile memories
    10.
    发明公开
    Steering gate and bit line segmentation in non-volatile memories 有权
    在einemnichtflüchtigenSpeicher的Segmentierung der Bitleitung und des Steuergates

    公开(公告)号：EP1610338A1

    公开(公告)日：2005-12-28

    申请号：EP05076921.5

    申请日：2002-03-29

    申请人： SanDisk Corporation

    发明人： Harari, Eliyahou ,  Samachisa, George ,  Guterman, Daniel C. ,  Yuan, Jack H.

    IPC分类号： G11C7/18 ,  G11C16/04 ,  G11C7/12

    CPC分类号： G11C7/18 ,  G11C7/12 ,  G11C16/0433 ,  G11C16/0458 ,  G11C16/0491

    摘要： Steering and bit lines (of a flash EEPROM system, for example) are segmented along columns of a memory cell array. In one embodiment, the steering and bit lines of one of their segments are connected at a time to respective global steering and bit lines. The number of rows of memory cells included in individual steering gate segments is a multiple of the number of rows included in individual bit line segments in order to have fewer steering gate segments. This saves considerable circuit area by reducing the number of segment selecting transistors necessary for the steering gates, since these transistors must be larger than those used to select bit line segments in order to handle higher voltages. In another embodiment, local steering gate line segments are combined in order to reduce their number, and the reduced number of each segment is then connected directly with an address decoder, without the necessity of a multiplicity of large switching transistors outside of the decoder to select the segment.

    摘要翻译： 转向和位线（例如，闪存EEPROM系统）沿着存储单元阵列的列进行分段。 在一个实施例中，其一个段的转向和位线一次连接到相应的全局转向和位线。 包括在各个转向门段中的存储单元的行数是单个位线段中包括的行数的倍数，以便具有较少的转向门段。 这通过减少转向门所需的段选择晶体管的数量来节省相当大的电路面积，因为这些晶体管必须大于用于选择位线段以用于处理更高电压的晶体管。 在另一个实施例中，组合本地导向栅极线段以便减少它们的数量，然后将每个段的减少的数量直接与地址解码器相连，而不需要在解码器之外的多个大的开关晶体管来选择 该段。