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    Steering gate and bit line segmentation in non-volatile memories
    1.
    发明公开
    Steering gate and bit line segmentation in non-volatile memories 有权
    在einemnichtflüchtigenSpeicher的Segmentierung der Bitleitung und des Steuergates

    公开(公告)号：EP1610338A1

    公开(公告)日：2005-12-28

    申请号：EP05076921.5

    申请日：2002-03-29

    申请人： SanDisk Corporation

    发明人： Harari, Eliyahou ,  Samachisa, George ,  Guterman, Daniel C. ,  Yuan, Jack H.

    IPC分类号： G11C7/18 ,  G11C16/04 ,  G11C7/12

    CPC分类号： G11C7/18 ,  G11C7/12 ,  G11C16/0433 ,  G11C16/0458 ,  G11C16/0491

    摘要： Steering and bit lines (of a flash EEPROM system, for example) are segmented along columns of a memory cell array. In one embodiment, the steering and bit lines of one of their segments are connected at a time to respective global steering and bit lines. The number of rows of memory cells included in individual steering gate segments is a multiple of the number of rows included in individual bit line segments in order to have fewer steering gate segments. This saves considerable circuit area by reducing the number of segment selecting transistors necessary for the steering gates, since these transistors must be larger than those used to select bit line segments in order to handle higher voltages. In another embodiment, local steering gate line segments are combined in order to reduce their number, and the reduced number of each segment is then connected directly with an address decoder, without the necessity of a multiplicity of large switching transistors outside of the decoder to select the segment.

    摘要翻译： 转向和位线（例如，闪存EEPROM系统）沿着存储单元阵列的列进行分段。 在一个实施例中，其一个段的转向和位线一次连接到相应的全局转向和位线。 包括在各个转向门段中的存储单元的行数是单个位线段中包括的行数的倍数，以便具有较少的转向门段。 这通过减少转向门所需的段选择晶体管的数量来节省相当大的电路面积，因为这些晶体管必须大于用于选择位线段以用于处理更高电压的晶体管。 在另一个实施例中，组合本地导向栅极线段以便减少它们的数量，然后将每个段的减少的数量直接与地址解码器相连，而不需要在解码器之外的多个大的开关晶体管来选择 该段。

    Steering gate and bit line segmentation in non-volatile memories
    2.
    发明公开
    Steering gate and bit line segmentation in non-volatile memories 审中-公开
    Stefergate- und Bitleitungssegmentierung innichtflüchtigenSpeichern

    公开(公告)号：EP2009643A1

    公开(公告)日：2008-12-31

    申请号：EP08014274.8

    申请日：2002-03-29

    申请人： SanDisk Corporation

    发明人： Harari, Eliyahou ,  Samachisa, George ,  Guterman, Daniel C. ,  Yuan, Jack H.

    IPC分类号： G11C7/18 ,  G11C16/04 ,  G11C7/12

    CPC分类号： G11C7/18 ,  G11C7/12 ,  G11C16/0433 ,  G11C16/0458 ,  G11C16/0491

    摘要： Steering and bit lines (of a flash EEPROM system, for example) are segmented along columns of a memory cell array. In one embodiment, the steering and bit lines of one of their segments are connected at a time to respective global steering and bit lines. The number of rows of memory cells included in individual steering gate segments is a multiple of the number of rows included in individual bit line segments in order to have fewer steering gate segments. This saves considerable circuit area by reducing the number of segment selecting transistors necessary for the steering gates, since these transistors must be larger than those used to select bit line segments in order to handle higher voltages. In another embodiment, local steering gate line segments are combined in order to reduce their number, and the reduced number of each segment is then connected directly with an address decoder, without the necessity of a multiplicity of large switching transistors outside of the decoder to select the segment.

    摘要翻译： 转向和位线（例如，闪存EEPROM系统）沿着存储单元阵列的列进行分段。 在一个实施例中，其一个段的转向和位线一次连接到相应的全局转向和位线。 包括在各个转向门段中的存储单元的行数是单个位线段中包括的行数的倍数，以便具有较少的转向门段。 这通过减少转向门所需的段选择晶体管的数量来节省相当大的电路面积，因为这些晶体管必须大于用于选择位线段以用于处理更高电压的晶体管。 在另一个实施例中，组合本地导向栅极线段以便减少它们的数量，然后将每个段的减少的数量直接与地址解码器相连，而不需要在解码器之外的多个大的开关晶体管来选择 该段。

    Writable tracking cells
    4.
    发明公开
    Writable tracking cells 有权
    可写追踪细胞

    公开(公告)号：EP1624461A3

    公开(公告)日：2006-07-12

    申请号：EP05077430.6

    申请日：2001-09-25

    申请人： SanDisk Corporation

    发明人： Gongwer, Geoffrey S. ,  Khalid, Shahzad B. ,  Guterman, Daniel C. ,  Simko, Richard ,  Conley, Kevin M.

    IPC分类号： G11C11/56 ,  G11C27/00

    CPC分类号： G11C16/28 ,  G11C7/06 ,  G11C11/56 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5642 ,  G11C27/005 ,  G11C2211/5621 ,  G11C2211/5634

    摘要： The present invention presents several techniques for using writable tracking cells. Multiple tracking cells are provided for each write block of the memory. These cells are re-programmed each time the user cells of the associated write block are written, preferably at the same time, using the same fixed, global reference levels to set the tracking and user cell programmed thresholds. The threshold voltages of the tracking cells are read every time the user cells are read, and these thresholds are used to determine the stored logic levels of the user cells. In one set of embodiments, populations of one or more tracking cells are associated with different logic levels of a multi-state memory. These tracking cell populations may be provided for only a subset of the logic levels. The read points for translating the threshold voltages are derived for all of the logic levels based upon this subset. In one embodiment, two populations each consisting of multiple tracking cells are associated with two logic levels of the multi-bit cell. In an analog implementation, the user cells are read directly using the analog threshold values of the tracking cell populations without their first being translated to digital values. A set of alternate embodiments provide for using different voltages and/or timing for the writing of tracking cells to provide less uncertainty in the tracking cells' final written thresholds.

    Reducing the effects of noise in non-volatile memories through multiple reads
    7.
    发明公开
    Reducing the effects of noise in non-volatile memories through multiple reads 有权
    的效果降低由噪声的非易失性存储器所造成的反复读出

    公开(公告)号：EP1329894A1

    公开(公告)日：2003-07-23

    申请号：EP03250294.0

    申请日：2003-01-17

    申请人： SanDisk Corporation

    发明人： Gonzalez, Carlos J. ,  Guterman, Daniel C.

    IPC分类号： G11C7/10 ,  G11C16/34

    CPC分类号： G11C7/106 ,  G11C7/1006 ,  G11C7/1051 ,  G11C16/12 ,  G11C16/26 ,  G11C16/28 ,  G11C16/3454 ,  G11C16/3459 ,  G11C2013/0057

    摘要： Storage elements are read multiple times and the results are accumulated and averaged for each storage element to reduce the effects of noise or other transients in the storage elements and associated circuits that may adversely affect the quality of the read. Several techniques may be employed, including: A full read and transfer of the data from the storage device to the controller device for each iteration, with averaging performed by the controller; a full read of the data for each iteration, with the averaging performed by the storage device, and no transfer to the controller until the final results arc obtained; one full read followed by a number of faster re-reads exploiting the already established state information to avoid a full read, followed by an intelligent algorithm to guide the state at which the storage element is sensed. These techniques may be used as the normal mode of operation, or invoked upon exception condition, depending on the system characteristics. A similar form of signal averaging may be employed during the verify phase of programming. An embodiment of this technique would use a peak-detection scheme. In this scenario, several verify checks are performed at the state prior to deciding if the storage element has reached the target state. If some predetermined portion of the verifies fail, the storage clement receives additional programming. These techniques allow the system to store more states per storage element in the presence of various sources of noise.

    摘要翻译： 存储元件被读取多次，结果累加和平均对于每个存储元件以减少在存储元件的噪声或其它瞬变的影响和相关联的电路可以产生不利的影响做了读取的质量。 几个技术可被采用，其中包括：对于每次迭代的完整的读取和从所述存储装置中的数据传送到控制器设备，由控制器执行的平均化; 对于每次迭代中的数据，与由所述存储装置执行的平均化，并没有传送到控制器，直至获得的最终结果弧的完整的读取; 一个完全的读其次一些更快的重新读取利用已经建立的状态信息，以避免完全读取，随后由智能算法来指导在其中，存储元件感测到的状态。 这些技术可以被用作操作的正常模式中，或在异常条件被调用，这取决于系统的特征。 可以在编程的验证阶段中采用的信号平均的类似形式。 这种技术的一个实施例，就可以使用峰值检测方案。 在这种情况下，几个验证检查是在状态存储元件是否已达到目标状态决定之前进行。 如果验证的一些预定部分发生故障，则存储接收克莱门特额外的编程。 这些技术允许系统每个存储元件存储多个状态中的噪声的各种源的存在。