公开(公告)号：EP2191508B1

公开(公告)日：2011-06-29

申请号：EP08836145.6

申请日：2008-09-26

申请人： Sandisk 3D LLC

发明人： TANAKA, Yoichiro ,  RADIGAN, Steven, J. ,  RAGHURAM, Usha

IPC分类号： H01L21/8229 ,  H01L27/102

CPC分类号： H01L27/101 ,  H01L27/1021

摘要： A semiconductor wafer assembly includes a base of dielectric. A layer of silicon is deposited thereover. A metal hard mask is deposited over the silicon. A dielectric hard mask is deposited over the metal hard mask. Photoresist is deposited over the dielectric hard mask, whereby a plurality of sacrificial columns is formed from the layer of metal hard mask through the photoresist such that the sacrificial columns extend out from the silicon layer. An interface layer is disposed between the layer of conductive material and the layer of hard mask to enhance adhesion between each of the plurality of sacrificial columns and the layer of conductive material to optimize the formation of junction diodes out of the silicon by preventing the plurality of sacrificial columns from being detached from the layer of silicon prematurely due to the sacrificial columns peeling or falling off.

公开(公告)号：EP2494586A2

公开(公告)日：2012-09-05

申请号：EP10774374.2

申请日：2010-10-26

申请人： Sandisk 3D LLC

发明人： SCHEUERLEIN, Roy, E. ,  TANAKA, Yoichiro

IPC分类号： H01L21/033

CPC分类号： G11C5/06 ,  H01L21/0337 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/101 ,  H01L27/2481 ,  H01L2924/0002 ,  Y10S257/909 ,  H01L2924/00

摘要： The present invention provides apparatus, methods, and systems for fabricating memory lines and structures using double sidewall patterning for four times half pitch relief patterning. The invention includes forming features from a first template layer disposed above a substrate, forming half-pitch sidewall spacers adjacent the features, forming smaller features in a second template layer by using the half-pitch sidewall spacers as a hardmask, forming quarter-pitch sidewall spacers adjacent the smaller features, and forming conductor features from a conductor layer by using the quarter-pitch sidewall spacers as a hardmask. Numerous additional aspects are disclosed.

公开(公告)号：EP2454754A2

公开(公告)日：2012-05-23

申请号：EP10734617.3

申请日：2010-07-13

申请人： SanDisk 3D LLC

发明人： MAKALA, Raghuveer ,  DUNTON, Vance ,  TANAKA, Yoichiro ,  MAXWELL, Steven ,  ZHANG, Tong ,  RADIGAN, Steven, J.

IPC分类号： H01L27/10 ,  H01L27/24

CPC分类号： H01L27/1021 ,  H01L27/101 ,  H01L27/2409 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/147 ,  H01L45/148 ,  H01L45/149 ,  H01L45/16

摘要： A method of making a semiconductor device includes forming a first layer comprising a seed material over an underlying layer, forming a second layer comprising a sacrificial material over the first layer, the sacrificial material being different from the seed material, patterning the first layer and the second layer into a plurality of separate features, forming an insulating filling material between the plurality of the separate features, removing the sacrificial material from the separate features to form a plurality of openings in the insulating filling material such that the seed material is exposed in the plurality of openings, and growing a semiconductor material on the exposed seed material in the plurality of openings.

公开(公告)号：EP2227825A2

公开(公告)日：2010-09-15

申请号：EP08870041.4

申请日：2008-12-30

申请人： Sandisk 3D LLC

发明人： SCHRICKER, April ,  CLARK, Mark ,  HERNER, Brad ,  TANAKA, Yoichiro

IPC分类号： H01L21/8247 ,  H01L27/11

CPC分类号： H01L51/0595 ,  B82Y10/00 ,  B82Y30/00 ,  B82Y40/00 ,  G11C13/0014 ,  G11C13/025 ,  G11C2213/71 ,  G11C2213/72 ,  H01L21/31053 ,  H01L27/1021 ,  H01L27/2409 ,  H01L27/2481 ,  H01L27/285 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/149 ,  H01L45/1616 ,  H01L51/0048 ,  H01L51/0587 ,  H01L51/0591

摘要： In some aspects, a method of fabricating a memory cell is provided that includes (1) fabricating a first conductor above a substrate; (2) fabricating a carbon nano- tube (CNT) material above the first conductor; (3) depositing a dielectric material onto a top surface of the CNT material; (4) planarizing the dielectric material to expose at least a portion of the CNT material; (5) fabricating a diode above the first conductor; and (6) fabricating a second conductor above the CNT material and the diode. Numerous other aspects are provided.

公开(公告)号：EP2191508A1

公开(公告)日：2010-06-02

申请号：EP08836145.6

申请日：2008-09-26

申请人： Sandisk 3D LLC

发明人： TANAKA, Yoichiro ,  RADIGAN, Steven, J. ,  RAGHURAM, Usha

IPC分类号： H01L27/102

CPC分类号： H01L27/101 ,  H01L27/1021

摘要： A semiconductor wafer assembly includes a base of dielectric. A layer of silicon is deposited thereover. A metal hard mask is deposited over the silicon. A dielectric hard mask is deposited over the metal hard mask. Photoresist is deposited over the dielectric hard mask, whereby a plurality of sacrificial columns is formed from the layer of metal hard mask through the photoresist such that the sacrificial columns extend out from the silicon layer. An interface layer is disposed between the layer of conductive material and the layer of hard mask to enhance adhesion between each of the plurality of sacrificial columns and the layer of conductive material to optimize the formation of junction diodes out of the silicon by preventing the plurality of sacrificial columns from being detached from the layer of silicon prematurely due to the sacrificial columns peeling or falling off.