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公开(公告)号：EP3408874A1
公开(公告)日：2018-12-05
申请号：EP17704524.2
申请日：2017-01-25
申请人： Arm Ltd
发明人： ARAUJO, Carlos Alberto Paz de , CELINSKA, Jolanta Bozena , REID, Kimberly Gay , SHIFREN, Lucian
CPC分类号： H01L45/1616 , C23C14/085 , C23C16/406 , C23C16/45527 , C23C16/45529 , C23C16/56 , G11C11/5678 , G11C13/0007 , G11C13/0011 , H01L45/04 , H01L45/122 , H01L45/1233 , H01L45/1253 , H01L45/146 , H01L45/147 , H01L45/1641
摘要： Subject matter disclosed herein may relate to fabrication of correlated electron materials used, for example, to perform a switching function. In embodiments, a correlated electron material may comprise a dominant ligand and a substitutional ligand, which may permit electron donation and back-donation in a correlated electron material. Electron donation and back-donation may enable the correlated electron material to exhibit a transition from high impedance/insulative state to a low impedance conductive state.
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公开(公告)号：EP3163577B1
公开(公告)日：2018-08-29
申请号：EP16189072.8
申请日：2015-05-20
IPC分类号： H01L27/24 , G11C7/18 , G11C13/00 , H01L45/00 , G11C29/02 , H01L29/786 , G11C16/24 , G11C16/26 , G11C16/08 , G11C16/10 , G11C7/12 , G06F11/10 , G11C29/12
CPC分类号： G11C13/004 , G06F11/1048 , G11C7/12 , G11C7/18 , G11C13/0002 , G11C13/0007 , G11C13/0021 , G11C13/0026 , G11C13/0028 , G11C13/0033 , G11C13/0069 , G11C13/0097 , G11C16/08 , G11C16/10 , G11C16/24 , G11C16/26 , G11C29/025 , G11C29/028 , G11C2029/1204 , G11C2213/71 , G11C2216/10 , H01L27/2436 , H01L27/2454 , H01L27/2481 , H01L27/249 , H01L29/786 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/122 , H01L45/1226 , H01L45/1246 , H01L45/146
摘要： Methods for reducing leakage currents through unselected memory cells of a memory array during a memory operation are described. In some cases, the leakage currents through the unselected memory cells of the memory array may be reduced by setting an adjustable resistance bit line structure connected to the unselected memory cells into a non-conducting state. The adjustable resistance bit line structure may comprise a bit line structure in which the resistance of an intrinsic (or near intrinsic) polysilicon portion of the bit line structure may be adjusted via an application of a voltage to a select gate portion of the bit line structure that is not directly connected to the intrinsic polysilicon portion. The intrinsic polysilicon portion may be set into a conducting state or a non-conducting state based on the voltage applied to the select gate portion.
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公开(公告)号：EP2927975B8
公开(公告)日：2018-08-15
申请号：EP14186833.1
申请日：2014-09-29
发明人： Ho, Chia-Hua , Chang, Shuo-Che , Liao, Hsiu-Han , Hsu, Po-Yen , Lin, Meng-Hung , Wu, Bo-Lun , Shen, Ting-Ying
IPC分类号： H01L45/00
CPC分类号： H01L45/1253 , H01L45/08 , H01L45/1233 , H01L45/146 , H01L45/16
摘要： Provided is a resistive random access memory including a first electrode layer (102), a second electrode layer (106), and a variable resistance layer (104) disposed between the first electrode layer and the second electrode layer, wherein the second electrode layer includes a first sublayer (108), a second sublayer (112), and a conductive metal oxynitride layer (110) disposed between the first sublayer and the second sublayer.
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公开(公告)号：EP3163576B1
公开(公告)日：2018-08-01
申请号：EP16189070.2
申请日：2015-05-20
IPC分类号： G11C7/18 , G11C13/00 , G11C7/12 , G11C16/08 , G11C16/10 , G11C16/24 , G11C16/26 , G11C29/02 , H01L27/24
CPC分类号： G11C13/004 , G06F11/1048 , G11C7/12 , G11C7/18 , G11C13/0002 , G11C13/0007 , G11C13/0021 , G11C13/0026 , G11C13/0028 , G11C13/0033 , G11C13/0069 , G11C13/0097 , G11C16/08 , G11C16/10 , G11C16/24 , G11C16/26 , G11C29/025 , G11C29/028 , G11C2029/1204 , G11C2213/71 , G11C2216/10 , H01L27/2436 , H01L27/2454 , H01L27/2481 , H01L27/249 , H01L29/786 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/122 , H01L45/1226 , H01L45/1246 , H01L45/146
摘要： Methods for reducing leakage currents through unselected memory cells of a memory array during a memory operation are described. In some cases, the leakage currents through the unselected memory cells of the memory array may be reduced by setting an adjustable resistance bit line structure connected to the unselected memory cells into a non-conducting state. The adjustable resistance bit line structure may comprise a bit line structure in which the resistance of an intrinsic (or near intrinsic) polysilicon portion of the bit line structure may be adjusted via an application of a voltage to a select gate portion of the bit line structure that is not directly connected to the intrinsic polysilicon portion. The intrinsic polysilicon portion may be set into a conducting state or a non-conducting state based on the voltage applied to the select gate portion.
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5.发明公开TECHNIQUES FOR FILAMENT LOCALIZATION, EDGE EFFECT REDUCTION, AND FORMING/SWITCHING VOLTAGE REDUCTION IN RRAM DEVICES 审中-公开RRAM器件中纤丝局部化，边缘效应减小以及形成/切换电压降低的技术
公开(公告)号：EP3320556A1
公开(公告)日：2018-05-16
申请号：EP16818561.9
申请日：2016-06-27
申请人： INTEL Corporation
发明人： PILLARISETTY, Ravi , MAJHI, Prashant , SHAH, Uday , MUKHERJEE, Niloy , KARPOV, Elijah , DOYLE, Brian , CHAU, Robert
CPC分类号： H01L45/122 , H01L45/08 , H01L45/1233 , H01L45/1246 , H01L45/1253 , H01L45/1273 , H01L45/146 , H01L45/1675
摘要： The present disclosure provides a system and method for forming a resistive random access memory (RRAM) device. A RRAM device consistent with the present disclosure includes a substrate and a first electrode disposed thereon. The RRAM device includes a second electrode disposed over the first electrode and a RRAM dielectric layer disposed between the first electrode and the second electrode. The RRAM dielectric layer has a recess at a top center portion at the interface between the second electrode and the RRAM dielectric layer.
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公开(公告)号：EP3314653A1
公开(公告)日：2018-05-02
申请号：EP15896511.1
申请日：2015-06-23
申请人： INTEL Corporation
发明人： KARPOV, Elijah V. (Ilya) , KAVALIEROS, Jack T. , CHAU, Robert S. , MUKHERJEE, Niloy , MAJHI, Prashant , LE, Van H. , PILLARISETTY, Ravi , SHAH, Uday , DEWEY, Gilbert , RADOSAVLJEVIC, Marko , RIOS, Rafael
IPC分类号： H01L27/108
CPC分类号： H01L27/108 , G11C13/0007 , H01L27/11551 , H01L27/1156 , H01L27/2436 , H01L27/2472 , H01L29/7869 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/145 , H01L45/146 , H01L45/148 , H01L45/1625 , H01L45/1633
摘要： A thin film transistor is deposited over a portion of a metal layer over a substrate. A memory element is coupled to the thin film transistor to provide a first memory cell. A second memory cell is over the first memory. A logic block is coupled to at least the first memory cell.
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公开(公告)号：EP3063009A4
公开(公告)日：2018-03-21
申请号：EP13896792
申请日：2013-10-31
发明人： YANG JIANHUA , GE NING , LI ZHIYONG
CPC分类号： H01L45/1633 , B41J2/04541 , B41J2/0458 , B41J2/14016 , B41J2/14072 , B41J2/14129 , B41J2/1601 , B41J2/1607 , B41J2/1626 , B41J2/1631 , B41J2202/13 , H01L21/02565 , H01L27/24 , H01L27/2463 , H01L45/00 , H01L45/04 , H01L45/08 , H01L45/145 , H01L45/146 , H01L45/147 , H01L45/1675
摘要： In some examples, an integrated circuit device includes a substrate, a memristor over the substrate and comprising a first metal layer as a first electrode, a second metal layer as a second electrode, and a switching oxide layer between the first and second metal layers, and a thermal resistor layer over the substrate.
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公开(公告)号：EP2943982B1
公开(公告)日：2018-03-14
申请号：EP13870616.3
申请日：2013-12-11
IPC分类号： H01L45/00
CPC分类号： H01L45/1616 , H01L45/04 , H01L45/085 , H01L45/1233 , H01L45/1253 , H01L45/1266 , H01L45/145 , H01L45/146 , H01L45/147
摘要： Some embodiments include a method of forming a memory cell. A first portion of a switching region is formed over a first electrode. A second portion of the switching region is formed over the first portion using atomic layer deposition. The second portion is a different composition than the first portion. An ion source region is formed over the switching region. A second electrode is formed over the ion source region. Some embodiments include a memory cell having a switching region between a pair of electrodes. The switching region is configured to be reversibly transitioned between a low resistive state and a high resistive state. The switching region includes two or more discrete portions, with one of the portions not having a non-oxygen component in common with any composition directly against it in the high resistive state.
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公开(公告)号：EP3238252A4
公开(公告)日：2017-12-27
申请号：EP14908603
申请日：2014-12-19
发明人： YANG JIANHUA , WILLIAMS STANLEY , ZHANG MAX , LI ZHIYONG
CPC分类号： H01L27/26 , H01L27/2409 , H01L27/2463 , H01L45/085 , H01L45/1233 , H01L45/146 , H01L47/005
摘要： A negative differential resistance (NDR) device for non-volatile memory cells in crossbar arrays is provided. Each non-volatile memory cell is situated at a crosspoint of the array. Each non-volatile memory cell comprises a switching layer in series with an NDR material containing fast diffusive atoms that are electrochemically inactive. The switching layer is positioned between two elec-trodes.
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公开(公告)号：EP2847794B1
公开(公告)日：2017-12-27
申请号：EP13787091.1
申请日：2013-05-07
发明人： SANDHU, Gurtej S.
IPC分类号： H01L45/00
CPC分类号： H01L45/1253 , G11C13/0002 , G11C13/0007 , G11C13/0011 , G11C13/0016 , G11C13/0069 , G11C2013/0083 , G11C2213/17 , G11C2213/18 , G11C2213/52 , G11C2213/53 , H01L45/08 , H01L45/085 , H01L45/1206 , H01L45/1233 , H01L45/14 , H01L45/141 , H01L45/142 , H01L45/143 , H01L45/146 , H01L45/147 , H01L45/16
摘要： Switching device structures and methods are described herein. A switching device can include a vertical stack comprising a material formed between a first and a second electrode. The switching device can further include a third electrode coupled to the vertical stack and configured to receive a voltage applied thereto to control a formation state of a conductive pathway in the material between the first and the second electrode, wherein the formation state of the conductive pathway is switchable between an on state and an off state.
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