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    Method of making a logic transistor and a non-volatile memory (nvm) cell
    1.
    发明授权
    Method of making a logic transistor and a non-volatile memory (nvm) cell 有权
    制造逻辑晶体管和非易失性存储器（nvm）单元的方法

    公开(公告)号：EP2725607B1

    公开(公告)日：2017-12-13

    申请号：EP13188538.6

    申请日：2013-10-14

    申请人： NXP USA, Inc.

    发明人： Shroff, Mehul ,  Hall, Mark D

    IPC分类号： H01L21/8239 ,  H01L27/105

    CPC分类号： H01L21/28273 ,  H01L21/28282 ,  H01L27/11534 ,  H01L27/11536 ,  H01L27/11573 ,  H01L29/66545

    摘要： An oxide-containing layer (18) is formed directly on a semiconductor layer (12) in an NVM region (14), and a first partial layer (20) of a first material is formed over the oxide-containing layer in the NVM region. A first high-K dielectric layer (22) is formed directly on the semiconductor layer in a logic region (16). A first conductive layer (24) is formed over the first dielectric layer in the logic region. A second partial layer (26) of the first material is formed directly on the first partial layer in the NVM region and over the first conductive layer in the logic region. A logic device is formed in the logic region. An NVM cell is formed in the NVM region, wherein the first and second partial layer together are used to form one of a charge storage layer (28) if the cell is a floating gate cell or a select gate (28) if the cell is a split gate cell.

    Method of making a logic transistor and a non-volatile memory (nvm) cell
    3.
    发明公开
    Method of making a logic transistor and a non-volatile memory (nvm) cell 有权
    一种用于制造逻辑晶体管和非易失性存储器（NVM）单元处理

    公开(公告)号：EP2725607A2

    公开(公告)日：2014-04-30

    申请号：EP13188538.6

    申请日：2013-10-14

    申请人： Freescale Semiconductor, Inc.

    发明人： Shroff, Mehul ,  Hall, Mark D

    IPC分类号： H01L21/8239 ,  H01L27/105

    CPC分类号： H01L21/28273 ,  H01L21/28282 ,  H01L27/11534 ,  H01L27/11536 ,  H01L27/11573 ,  H01L29/66545

    摘要： An oxide-containing layer (18) is formed directly on a semiconductor layer (12) in an NVM region (14), and a first partial layer (20) of a first material is formed over the oxide-containing layer in the NVM region. A first high-K dielectric layer (22) is formed directly on the semiconductor layer in a logic region (16). A first conductive layer (24) is formed over the first dielectric layer in the logic region. A second partial layer (26) of the first material is formed directly on the first partial layer in the NVM region and over the first conductive layer in the logic region. A logic device is formed in the logic region. An NVM cell is formed in the NVM region, wherein the first and second partial layer together are used to form one of a charge storage layer (28) if the cell is a floating gate cell or a select gate (28) if the cell is a split gate cell.

    Integrated flash memory, peripheral circuit and manufacture method
    7.
    发明公开
    Integrated flash memory, peripheral circuit and manufacture method 有权
    集成闪存，外围电路和制造工艺

    公开(公告)号：EP1708266A3

    公开(公告)日：2008-10-29

    申请号：EP05254538.1

    申请日：2005-07-20

    申请人： FUJITSU LIMITED

    发明人： Nakagawa, Shinichi, Fujitsu Limited

    IPC分类号： H01L27/105 ,  H01L21/8247 ,  H01L27/115

    CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11536 ,  H01L27/11548

    摘要： A non-volatile semiconductor memory device includes: a non-volatile memory area including gate electrodes, each including stack of a floating gate, an inter-electrode insulating film and a control gate, and having first insulating side walls formed on side walls of the gate electrode; a peripheral circuit area including single-layer gate electrodes made of the same layer as the control gate; and a first border area including: a first isolation region formed in the semiconductor substrate for isolating the non-volatile memory area and peripheral circuit area; a first conductive pattern including a portion made of the same layer as the control gate and formed above the isolation region; and a first redundant insulating side wall made of the same layer as the first insulating side wall and formed on the side wall of the first conductive pattern on the side of the non-volatile memory area.

    Sealing method for electronic devices formed on a common semiconductor substrate and corresponding circuit structure
    8.
    发明公开
    Sealing method for electronic devices formed on a common semiconductor substrate and corresponding circuit structure 有权
    Versegelungsverfahrenfürauf einem gemeinsamen Substrat hergestellte elektronische Bauelemente

    公开(公告)号：EP1526568A1

    公开(公告)日：2005-04-27

    申请号：EP03425687.5

    申请日：2003-10-22

    申请人： STMicroelectronics S.r.l.

    发明人： Camerlenghi, Emilio ,  Maurelli, Alfonso ,  Peschiaroli, Daniela ,  Zabberoni, Paola

    IPC分类号： H01L21/8247 ,  H01L21/8234

    CPC分类号： H01L27/11526 ,  H01L21/823468 ,  H01L23/3192 ,  H01L27/105 ,  H01L27/11536 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A sealing method for electronic devices such as flash memory cells (4) and CMOS transistors (5) formed on a common semiconductor substrate (1) comprising the steps of:

    forming at least a first conductive layer (7,9) on a first portion of semiconductor substrate (1),
    forming a second conductive layer (11) on a second portion of semiconductor substrate (1),
    defining a first plurality of gate regions (4a) of the memory cells (4) in at least a first conductive layer (7),
    forming a first sealing layer (14) on the whole semiconductor substrate (1) to seal the first plurality of gate regions (4a),
    defining a second plurality of gate regions (5a) of the CMOS transistors (5) in the second conductive layer (11),
    forming a second sealing layer (16) on the whole semiconductor substrate (1) to seal the second plurality of gate regions (5a).

    摘要翻译： 用于密封形成在半导体衬底上的电子器件的方法包括：形成与半导体衬底的第一部分相邻的多个第一电子器件，其中每个第一电子器件包括包含从半导体衬底突出的至少一个第一导电层的第一区域。 邻近第一区域形成第一密封层，用于密封多个第一电子器件。 在第一密封层附近形成保护层。 蚀刻保护层以形成与第一区域的侧壁相邻的保护性间隔物。 该方法还包括在半导体衬底的第二部分附近形成多个第二电子器件，每个第二电子器件包括第二区域，该第二区域包括从半导体衬底突出的第二导电层。 第二密封层邻近第二区域形成，用于密封多个第二电子器件，并邻近第一密封层以密封多个第一电子器件。

    Process for manufacturing electronic devices comprising non-volatile memory cells
    10.
    发明公开
    Process for manufacturing electronic devices comprising non-volatile memory cells 审中-公开
    Herstellungsverfahren elektronischer Bauelemente die Festwertspeicherzellen beinhalten

    公开(公告)号：EP1104023A1

    公开(公告)日：2001-05-30

    申请号：EP99830735.9

    申请日：1999-11-26

    申请人： STMicroelectronics S.r.l.

    发明人： Grossi, Alessandro ,  Clementi, Cesare

    IPC分类号： H01L21/8247 ,  H01L21/8239 ,  H01L27/115

    CPC分类号： H01L27/11526 ,  H01L27/1052 ,  H01L27/115 ,  H01L27/11517 ,  H01L27/11536

    摘要： The process for the manufacturing electronic devices including memory cells (72) comprises the steps of: forming, on a substrate (2) of semiconductor material, multilayer stacks (54) including a floating gate region (40a), an intermediate dielectric region (41a), and a control gate region (50a); forming a protective layer (75) extending on top of the substrate (2) and between the multilayer stacks (54) and having a height at least equal to the multilayer stacks. The step of forming multilayer stacks (54) comprises the step of defining the control gate region (50a) on all sides so that each control gate region is completely separate from adjacent control gate regions. The protective layer (75) isolates the multilayer stacks (54) from each other at the sides. Word lines (80a) of metal extend above the protective layer (75) and are in electrical contact with the gate regions.

    摘要翻译： 包括存储单元（72）的制造电子器件的方法包括以下步骤：在半导体材料的衬底（2）上形成包括浮动栅极区（40a），中间介电区（41a）的多层堆叠（54） ）和控制栅极区（50a）; 形成在衬底（2）的顶部和多层堆叠（54）之间延伸并具有至少等于多层堆叠的高度的保护层（75）。 形成多层堆叠（54）的步骤包括在所有侧面上限定控制栅极区域（50a）的步骤，使得每个控制栅极区域与相邻的控制栅极区域完全分离。 保护层（75）将多层堆叠（54）在侧面彼此隔离。 金属字线（80a）在保护层（75）上方延伸并与栅极区域电接触。