公开(公告)号：EP3262683A1

公开(公告)日：2018-01-03

申请号：EP16706290.0

申请日：2016-02-05

Applicant: Silicon Storage Technology Inc.

Inventor： KIM, Jinho ,  TIWARI, Vipin ,  DO, Nhan ,  LIU, Xian ,  QIAN, Xiaozhou ,  BAI, Ning ,  YUE, Kai Man

IPC: H01L27/112 ,  G11C16/04 ,  G11C17/12 ,  H01L27/115 ,  H01L29/423

CPC classification number: H01L27/11524 ,  H01L23/57 ,  H01L27/11226 ,  H01L27/11233 ,  H01L27/11253 ,  H01L27/11519 ,  H01L29/42328 ,  H01L29/788 ,  H01L29/7881

Abstract: A memory device that includes a plurality of ROM cells each having spaced apart source and drain regions formed in a substrate with a channel region therebetween, a first gate disposed over and insulated from a first portion of the channel region, a second gate disposed over and insulated from a second portion of the channel region, and a conductive line extending over the plurality of ROM cells. The conductive line is electrically coupled to the drain regions of a first subgroup of the ROM cells, and is not electrically coupled to the drain regions of a second subgroup of the ROM cells. Alternately, a first subgroup of the ROM cells each includes a higher voltage threshold implant region in the channel region, whereas a second subgroup of the ROM cells each lack any higher voltage threshold implant region in the channel region.

公开(公告)号：EP4107728A1

公开(公告)日：2022-12-28

申请号：EP20775100.9

申请日：2020-08-31

Applicant: Silicon Storage Technology Inc.

Inventor： LIN, Guangming ,  QIAN, Xiaozhou ,  PI, Xiao Yan ,  TIWARI, Vipin ,  DING, Zhenlin

IPC: G11C16/34 ,  G06F12/02

公开(公告)号：EP4066381A1

公开(公告)日：2022-10-05

申请号：EP20722769.5

申请日：2020-04-03

Applicant: SILICON STORAGE TECHNOLOGY, INC.

Inventor： MEI, Ryan ,  QIAN, Xiaozhou ,  TRAN, Hieu Van ,  ZHU, Claire

IPC: H03K3/356

公开(公告)号：EP4032089A1

公开(公告)日：2022-07-27

申请号：EP20717431.9

申请日：2020-03-11

Applicant: Silicon Storage Technology Inc.

Inventor： QIAN, Xiaozhou ,  PI, Xiao Yan ,  TIWARI, Vipin

IPC: G11C16/16 ,  G11C16/10 ,  G11C16/34 ,  G11C11/56 ,  G11C7/22

公开(公告)号：EP2831885B1

公开(公告)日：2018-10-31

申请号：EP13767473.5

申请日：2013-03-15

Applicant: Silicon Storage Technology Inc.

Inventor： ZHOU, Yao ,  QIAN, Xiaozhou ,  BAI, Ning

IPC: G11C16/28 ,  G11C11/56 ,  G11C16/08 ,  G11C16/26 ,  G11C7/06

CPC classification number: G11C16/26 ,  G11C7/062 ,  G11C11/5642 ,  G11C16/08 ,  G11C16/28 ,  G11C2207/063

Abstract: A non-volatile memory device with a current injection sensing amplifier is disclosed.

公开(公告)号：EP2831877B1

公开(公告)日：2017-05-31

申请号：EP13769357.8

申请日：2013-03-15

Applicant: Silicon Storage Technology Inc.

Inventor： ZHOU, Yao ,  QIAN, Xiaozhou

IPC: G11C7/06 ,  G11C16/26 ,  G11C7/08

CPC classification number: G11C7/08 ,  G11C7/062 ,  G11C16/26 ,  G11C2207/002 ,  G11C2207/2254

公开(公告)号：EP4413572A1

公开(公告)日：2024-08-14

申请号：EP22709890.2

申请日：2022-02-23

Applicant: Silicon Storage Technology Inc.

Inventor： QIAN, Xiaozhou ,  ZHU, Yaohua

IPC: G11C29/02

CPC classification number: G11C29/024 ,  G11C29/025 ,  G11C2029/120220130101 ,  G11C17/00

公开(公告)号：EP2973570B1

公开(公告)日：2018-05-16

申请号：EP13878102.6

申请日：2013-03-15

Applicant: Silicon Storage Technology Inc.

Inventor： ZHOU, Yao ,  YUE, Kaiman ,  QIAN, Xiaozhou ,  SHENG, Bin

IPC: G11C7/08 ,  G11C7/22

CPC classification number: G11C16/28 ,  G11C7/08 ,  G11C7/227 ,  G11C8/18 ,  G11C16/24 ,  G11C16/26 ,  G11C16/32

Abstract: A self-timer for a sense amplifier in a memory device is disclosed.

公开(公告)号：EP2912662B1

公开(公告)日：2017-12-06

申请号：EP13779674.4

申请日：2013-10-03

Applicant: Silicon Storage Technology Inc.

Inventor： ZHOU, Yao ,  QIAN, Xiaozhou ,  LIN, Guangming

IPC: G11C7/06 ,  G11C16/28

CPC classification number: G11C11/5642 ,  G05F3/262 ,  G11C5/147 ,  G11C7/062 ,  G11C7/12 ,  G11C16/28 ,  G11C2207/063

公开(公告)号：EP3172733A1

公开(公告)日：2017-05-31

申请号：EP15731210.9

申请日：2015-06-11

Applicant: Silicon Storage Technology Inc.

Inventor： KIM, Jinho ,  DO, Nhan ,  TKACHEV, Yuri ,  YUE, Kai Man ,  QIAN, Xiaozhou ,  BAI, Ning

IPC: G11C16/16 ,  G11C16/04

CPC classification number: G11C16/14 ,  G11C16/0425 ,  G11C16/12 ,  G11C16/16 ,  G11C29/021 ,  G11C29/028

Abstract: A system and method to inhibit the erasing of a portion of a sector of split gate flash memory cells while allowing the remainder of the sector to be erased is disclosed. The inhibiting is controlled by control logic that applies one or more bias voltages to the portion of the sector whose erasure is to be inhibited.

Abstract translation: 公开了一种系统和方法，用于在允许擦除扇区的其余部分的同时禁止擦除分离栅极闪存单元的一部分扇区。 该抑制由控制逻辑控制，该控制逻辑将一个或多个偏置电压施加到擦除将被禁止的扇区的部分。