公开(公告)号：EP3178111A1

公开(公告)日：2017-06-14

申请号：EP15747281.2

申请日：2015-07-13

申请人： Silicon Storage Technology Inc.

发明人： YANG, Jeng-wei ,  WU, Man-tang ,  CHEN, Chun-ming ,  SU, Chien-sheng ,  DO, Nhan

IPC分类号： H01L27/115 ,  H01L29/423 ,  H01L29/788

CPC分类号： H01L27/11521 ,  H01L29/42328 ,  H01L29/7881

摘要： A non-volatile memory cell includes a semiconductor substrate of first conductivity type, first and second spaced-apart regions in the substrate of second conductivity type, with a channel region in the substrate therebetween. A floating gate has a first portion disposed vertically over a first portion of the channel region, and a second portion disposed vertically over the first region. The floating gate includes a sloping upper surface that terminates with one or more sharp edges. An erase gate is disposed vertically over the floating gate with the one or more sharp edges facing the erase gate. A control gate has a first portion disposed laterally adjacent to the floating gate, and vertically over the first region. A select gate has a first portion disposed vertically over a second portion of the channel region, and laterally adjacent to the floating gate.

摘要翻译： 一种非易失性存储器单元包括第一导电类型的半导体衬底，之间的第一和第二间隔开的区域中的第二导电类型的底物，具有沟道区中在基板那里。 浮置栅极具有在所述沟道区的第一部分垂直设置的第一部分，和第二部分垂直设置在所述第一区域。 浮栅包括一个倾斜的上表面上没有终止与一个或多个尖锐的边缘。 擦除栅极与上面对所述擦除栅的一个或多个尖锐的边缘的浮栅垂直设置。 控制栅极具有第一部分处理完毕迟到反弹邻近浮置栅极，以及垂直地在所述第一区域。 甲选择栅极具有在所述沟道区的第二部分垂直设置的第一部分，和晚期反弹邻近浮置栅极。

公开(公告)号：EP3243220A1

公开(公告)日：2017-11-15

申请号：EP15819943.0

申请日：2015-12-08

申请人： Silicon Storage Technology Inc.

发明人： CHEN, Chun-ming ,  WU, Man-tang ,  YANG, Jeng-wei ,  SU, Chien-sheng

IPC分类号： H01L29/423 ,  H01L29/66 ,  H01L29/788 ,  H01L27/115

CPC分类号： H01L27/11521 ,  H01L21/02181 ,  H01L21/02186 ,  H01L21/02189 ,  H01L21/28273 ,  H01L27/11524 ,  H01L29/42328 ,  H01L29/45 ,  H01L29/4916 ,  H01L29/495 ,  H01L29/511 ,  H01L29/517 ,  H01L29/66825 ,  H01L29/788 ,  H01L29/7881

摘要： A non-volatile memory cell includes a substrate of a first conductivity type, having a first region of a second conductivity type, a second region of the second conductivity type spaced apart from the first region, forming a channel region therebetween. A floating gate is disposed over and insulated from a first portion of the channel region which is adjacent the first region. A select gate is disposed over a second portion of the channel region adjacent to the second region, the select gate being formed of a metal material and being insulated from the second portion of the channel region by a layer of silicon dioxide and a layer of high K insulating material. A control gate is disposed over and insulated from the floating gate. An erase gate is disposed over and insulated from the first region, and disposed laterally adjacent to and insulated from the floating gate.