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公开(公告)号：EP0630109A2
公开(公告)日：1994-12-21
申请号：EP94304451.1
申请日：1994-06-20
IPC分类号： H03K19/0175 , H03K19/003
CPC分类号： H03K19/00315 , H03K19/0136 , H03K19/017518
摘要： A low-voltage output driving circuit capable of preventing the generation of leakage current. The circuit includes a transfer gate GT installed between the output S₂ of a first CMOS inverter INV C1 and the node S₁ at the gate of an MOS transistor PT₃ for active pull-up. At the same time, a reference voltage V REF and a voltage level V OUT , which corresponds to the voltage level of the output line of the signal S OUT , are compared by a comparator CMP. When the voltage V OUT is lower than the reference voltage V REF , the transfer gate GT is set to the ON state, and the output of the first CMOS inverter INV C1 is sent to the gate of the transistor PT₃ for active pull-up. The comparator CMP is installed so that when the voltage level V OUT is higher than the reference voltage V REF , the output of the first CMOS inverter INV C1 is prevented from reaching the gate of the transistor PT₃ for active pull-up. Thus, although the input and output can take on any state, the generation of leakage current which flows toward the power supply from the output side can be prevented.
摘要翻译： 一种能够防止产生漏电流的低压输出驱动电路。 该电路包括安装在第一CMOS反相器INVC1的输出S2和用于主动上拉的MOS晶体管PT3的栅极处的节点S1之间的传输门GT。 同时，通过比较器CMP比较对应于信号SOUT的输出线的电压电平的参考电压VREF和电压电平VOUT。 当电压VOUT低于参考电压VREF时，传输门GT被设置为导通状态，并且第一CMOS反相器INVC1的输出被发送到晶体管PT3的栅极用于主动上拉。 安装比较器CMP使得当电压电平VOUT高于参考电压VREF时，防止第一CMOS反相器INVC1的输出到达用于主动上拉的晶体管PT3的栅极。 因此，尽管输入和输出可以处于任何状态，但是可以防止从输出侧流向电源的泄漏电流的产生。
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公开(公告)号：EP0630109A3
公开(公告)日：1996-03-06
申请号：EP94304451.1
申请日：1994-06-20
IPC分类号： H03K19/0175 , H03K19/003
CPC分类号： H03K19/00315 , H03K19/0136 , H03K19/017518
摘要： A low-voltage output driving circuit capable of preventing the generation of leakage current. The circuit includes a transfer gate GT installed between the output S₂ of a first CMOS inverter INV C1 and the node S₁ at the gate of an MOS transistor PT₃ for active pull-up. At the same time, a reference voltage V REF and a voltage level V OUT , which corresponds to the voltage level of the output line of the signal S OUT , are compared by a comparator CMP. When the voltage V OUT is lower than the reference voltage V REF , the transfer gate GT is set to the ON state, and the output of the first CMOS inverter INV C1 is sent to the gate of the transistor PT₃ for active pull-up. The comparator CMP is installed so that when the voltage level V OUT is higher than the reference voltage V REF , the output of the first CMOS inverter INV C1 is prevented from reaching the gate of the transistor PT₃ for active pull-up. Thus, although the input and output can take on any state, the generation of leakage current which flows toward the power supply from the output side can be prevented.
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公开(公告)号：EP0630109B1
公开(公告)日：1998-08-26
申请号：EP94304451.1
申请日：1994-06-20
IPC分类号： H03K19/0175 , H03K19/003
CPC分类号： H03K19/00315 , H03K19/0136 , H03K19/017518
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