公开(公告)号：EP0681296B1

公开(公告)日：2001-09-19

申请号：EP95106827.9

申请日：1995-05-05

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Schreck, John F. ,  Kaya, Cetin

IPC: G11C16/06 ,  H02M3/07

CPC classification number: G11C16/30 ,  G11C16/12 ,  G11C16/16

公开(公告)号：EP0848384A2

公开(公告)日：1998-06-17

申请号：EP97121895.3

申请日：1997-12-12

Applicant: Texas Instruments Incorporated

Inventor： Kaya, Cetin

IPC: G11C16/04 ,  G11C16/06

CPC classification number: G11C16/10 ,  G11C16/0416

Abstract: A CHE programmed memory device (30) avoids forward biasing at an isolated P-well (38) junction with a deep N-well (36) and prevents emitting electrons that may cause voltage buildup across the isolated P-well region (38) by applying a forward bias current (50) or voltage source (40) connected to the deep N-well region (36) for slightly forward biasing the deep N-well region. This maintains the voltage drop of isolated P-well region (38) below the diode turn-on voltage.

Abstract translation: CHE编程存储器件（30）避免了在与深N阱（36）的隔离P阱（38）结处的正向偏置，并且防止可能通过分离的P阱区域（38）引起电压累积的电子发射 施加连接到深N阱区域（36）的正向偏置电流（50）或电压源（40）以略微向前偏置深N阱区域。 这将保持隔离P阱区（38）的电压降低于二极管导通电压以下。

公开(公告)号：EP0495492A2

公开(公告)日：1992-07-22

申请号：EP92100657.3

申请日：1992-01-16

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Kaya, Cetin ,  Tigelaar, Howard

IPC: G11C16/04 ,  H01L29/788 ,  G11C16/06 ,  H01L21/28

CPC classification number: G11C16/0425 ,  H01L29/42324 ,  H01L29/7885 ,  Y10S438/981

Abstract: A non-volatile split-gate memory cell 8 which can be programmed with only a five volt power supply and is fabricated using standard transistor processing methods, comprises a semiconductor substrate 10 with a source 12 and a drain 14 region separated by a channel region 16. A conductive floating gate 18 is formed over a portion 16a of the channel region 16 and separated by a FAMOS oxide 20. A conductive control gate 22 is formed over but electrically insulated from the floating gate 18 and over a second portion 16b of the channel region 16. The control gate 22 is separated from the second portion of the channel 16b by a pass oxide 26 which is thicker than the FAMOS oxide 20. Other embodiments and processes are also disclosed.

Abstract translation: 可以仅使用五伏电源编程并且使用标准晶体管处理方法制造的非易失性分裂栅极存储单元8包括半导体衬底10，其源极12和漏极14区域被沟道区域16分隔开 导电浮栅18形成在沟道区16的一部分16a上并由FAMOS氧化物20隔开。导电控制栅极22形成在与浮栅18并且在沟道的第二部分16b之上但与之电绝缘 控制栅极22通过比FAMOS氧化物20更厚的通过氧化物26与通道16b的第二部分分离。还公开了其他实施方案和方法。

公开(公告)号：EP0848384A3

公开(公告)日：1999-08-11

申请号：EP97121895.3

申请日：1997-12-12

Applicant: Texas Instruments Incorporated

Inventor： Kaya, Cetin

IPC: G11C16/04 ,  G11C16/06

CPC classification number: G11C16/10 ,  G11C16/0416

Abstract: A CHE programmed memory device (30) avoids forward biasing at an isolated P-well (38) junction with a deep N-well (36) and prevents emitting electrons that may cause voltage buildup across the isolated P-well region (38) by applying a forward bias current (50) or voltage source (40) connected to the deep N-well region (36) for slightly forward biasing the deep N-well region. This maintains the voltage drop of isolated P-well region (38) below the diode turn-on voltage.

Abstract translation: CHE编程的存储器装置（30）避免了在具有深N阱（36）的隔离的P阱（38）结处的正向偏置，并且防止了可能导致跨隔离P阱区（38） 施加连接到深N阱区（36）的正向偏置电流（50）或电压源（40）以略微正向偏置深N阱区。 这保持了隔离P阱区（38）的电压降低于二极管导通电压。

公开(公告)号：EP0836196A3

公开(公告)日：1999-06-09

申请号：EP97117402.4

申请日：1997-10-08

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： San, Kemal T. ,  Kaya, Cetin ,  Mehrad, Freidoon

IPC: G11C16/06 ,  G11C29/00

CPC classification number: G11C16/3409 ,  G06F2201/81 ,  G11C16/04 ,  G11C16/16 ,  G11C16/3404 ,  G11C16/3445 ,  G11C29/028 ,  G11C29/50 ,  G11C29/50004 ,  G11C2029/5006

Abstract: A system for testing and adjusting threshold voltages in flash EEPROMs is disclosed. The system includes a memory cell array (5) comprising a plurality of cell columns. Each cell column includes a plurality of memory cells (10). Each memory cell (10) has a control gate terminal (14), a drain terminal (12) and a source terminal 11. A control system comprising a wordline decoder (16), a column decoder (19) and a microprocessor (21) applies selected voltages to the respective terminals of the memory cells (10), and selects one of the plurality of cell columns for compaction verification. A detector (30) determines whether any one of the memory cells (10) of the selected cell column has a threshold voltage below a predetermined positive voltage, and supplies an output signal to the control system. The control system increases respective threshold voltages of the memory cells (10) of the selected cell column in response to the output signal of the detector (30).

公开(公告)号：EP0913862A1

公开(公告)日：1999-05-06

申请号：EP98308797.4

申请日：1998-10-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Kaya, Cetin ,  Ashburn, Staton P.

IPC: H01L21/8239

CPC classification number: H01L27/11526 ,  H01L27/105 ,  H01L27/11546

Abstract: The invention comprises an integrated circuit (100) including integral high and low-voltage peripheral transistors and a method for making the integrated circuit. In one aspect of the invention, a method of integrating high and low voltage transistors into a floating gate memory array comprises the steps of forming a tunnel oxide layer (24) outwardly from a semiconductor substrate (116), forming a floating gate layer (26) disposed outwardly from the tunnel oxide layer (24) and forming an insulator layer (28) disposed outwardly from the floating gate layer (26) to create a first intermediate structure. The method further includes the steps of masking a first region (114) and a second region (110) of the first intermediate structure leaving a third region (112) unmasked, removing at least a portion of the insulator layer (28), the floating gate layer (26) and the tunnel oxide layer (24) from the third region (112) and forming a first dielectric layer (42) disposed outwardly from the substrate (116) in a region approximately coextensive with the third region (112). The second region (110) and the third region (112) are masked, leaving the first region (114) unmasked. Then, at least a portion of the insulator layer (28), the floating gate layer (26) and the tunnel oxide layer (24) is removed from the first region (114) . A second dielectric layer (44) is formed outwardly from the substrate (116) and the first dielectric layer (42) in a region approximately coextensive with the first region (114) and the third regions (112), respectively.

Abstract translation: 本发明包括集成电路（100），其包括集成的高电压和低电压外围晶体管以及用于制造集成电路的方法。 在本发明的一个方面，将高压和低压晶体管集成到浮动栅极存储器阵列中的方法包括以下步骤：从半导体衬底（116）向外形成隧道氧化物层（24），形成浮栅（26） ），从隧道氧化物层（24）向外设置并形成从浮动栅极层（26）向外设置的绝缘体层（28），以形成第一中间结构。 该方法还包括以下步骤：掩蔽第一中间结构的第一区域（114）和第二区域（110），离开未屏蔽的第三区域（112），去除绝缘体层（28）的至少一部分，浮动 栅极层（26）和隧道氧化物层（24），并且形成在与第三区域（112）大致共同延伸的区域中从衬底（116）向外设置的第一介电层（42）。 掩蔽第二区域（110）和第三区域（112），使第一区域（114）不被屏蔽。 然后，从第一区域（114）去除绝缘体层（28），浮动栅极层（26）和隧道氧化物层（24）的至少一部分。 在与第一区域（114）和第三区域（112）分别大致共同延伸的区域中，从衬底（116）和第一介电层（42）向外形成第二介电层（44）。

公开(公告)号：EP0463331A3

公开(公告)日：1992-12-23

申请号：EP91107385.6

申请日：1991-05-07

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Kaya, Cetin

IPC: G11C16/06 ,  G11C11/40

CPC classification number: G11C16/10 ,  G11C16/32

Abstract: An improved method is provided for programming a non-volatile memory cell formed at a face of a layer of semiconductor 12 of a first conductivity type and having a source region 14 in a drain 16 of a second conductivity type spaced by a channel 18. A floating gate 22 is disposed insulatively adjacent channel 18 and a control gate 24 is disposed insulatively adjacent floating gate 22. The source region 14 is grounded while a first voltage is applied to the drain region 16. A time varying voltage pulse is applied to the control gate such that the potential of floating gate 22 remains substantially constant as electrons are accumulated on floating gate 22.

Abstract translation: 提供了一种改进的方法来编程形成在第一导电类型的半导体层12的表面处的非易失性存储单元，并且在由通道18隔开的第二导电类型的漏极16中具有源极区14。 浮置栅极22绝缘地邻近沟道18设置，并且控制栅极24与隔离栅极22隔离地设置。源极区域14接地，同时向漏极区域16施加第一电压。时变电压脉冲施加到控制 使得当浮置栅极22上的电子积累时，浮置栅极22的电位保持基本恒定

公开(公告)号：EP0836196B1

公开(公告)日：2006-05-24

申请号：EP97117402.4

申请日：1997-10-08

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： San, Kemal T. ,  Kaya, Cetin ,  Mehrad, Freidoon

IPC: G11C16/06 ,  G11C29/00

CPC classification number: G11C16/3409 ,  G06F2201/81 ,  G11C16/04 ,  G11C16/16 ,  G11C16/3404 ,  G11C16/3445 ,  G11C29/028 ,  G11C29/50 ,  G11C29/50004 ,  G11C2029/5006

Abstract: A system for testing and adjusting threshold voltages in flash EEPROMs is disclosed. The system includes a memory cell array (5) comprising a plurality of cell columns. Each cell column includes a plurality of memory cells (10). Each memory cell (10) has a control gate terminal (14), a drain terminal (12) and a source terminal 11. A control system comprising a wordline decoder (16), a column decoder (19) and a microprocessor (21) applies selected voltages to the respective terminals of the memory cells (10), and selects one of the plurality of cell columns for compaction verification. A detector (30) determines whether any one of the memory cells (10) of the selected cell column has a threshold voltage below a predetermined positive voltage, and supplies an output signal to the control system. The control system increases respective threshold voltages of the memory cells (10) of the selected cell column in response to the output signal of the detector (30).

公开(公告)号：EP0836196A2

公开(公告)日：1998-04-15

申请号：EP97117402.4

申请日：1997-10-08

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： San, Kemal T. ,  Kaya, Cetin ,  Mehrad, Freidoon

IPC: G11C16/06 ,  G11C29/00

CPC classification number: G11C16/3409 ,  G06F2201/81 ,  G11C16/04 ,  G11C16/16 ,  G11C16/3404 ,  G11C16/3445 ,  G11C29/028 ,  G11C29/50 ,  G11C29/50004 ,  G11C2029/5006

Abstract: A system for testing and adjusting threshold voltages in flash EEPROMs is disclosed. The system includes a memory cell array (5) comprising a plurality of cell columns. Each cell column includes a plurality of memory cells (10). Each memory cell (10) has a control gate terminal (14), a drain terminal (12) and a source terminal 11. A control system comprising a wordline decoder (16), a column decoder (19) and a microprocessor (21) applies selected voltages to the respective terminals of the memory cells (10), and selects one of the plurality of cell columns for compaction verification. A detector (30) determines whether any one of the memory cells (10) of the selected cell column has a threshold voltage below a predetermined positive voltage, and supplies an output signal to the control system. The control system increases respective threshold voltages of the memory cells (10) of the selected cell column in response to the output signal of the detector (30).

Abstract translation: 公开了一种用于测试和调整闪速EEPROM中的阈值电压的系统。 该系统包括包括多个单元列的存储单元阵列（5）。 每个单元列包括多个存储单元（10）。 每个存储单元（10）具有控制栅极端子（14），漏极端子（12）和源极端子11.一种包括字线解码器（16），列解码器（19）和微处理器（21）的控制系统， 将选择的电压施加到存储器单元（10）的各个端子，并且选择多个单元格列之一进行压缩验证。 检测器（30）确定所选单元列的存储单元（10）中的任何一个是否具有低于预定正电压的阈值电压，并将输出信号提供给控制系统。 响应于检测器（30）的输出信号，控制系统增加所选单元列的存储单元（10）的相应阈值电压。

公开(公告)号：EP0661718A3

公开(公告)日：1995-11-02

申请号：EP94112633.6

申请日：1994-08-12

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Kaya, Cetin ,  Holland, Wayland B. ,  Mezenner, Rabah

IPC: G11C16/06

CPC classification number: G11C16/16

Abstract: The erasing method of this invention results in a relatively narrow distribution of threshold voltages when used to flash erase a group of floating-gate-type memory cells ( 10 ). Each cell includes a control gate ( 14 ), a source ( 11 ) and a drain ( 12 ). The method comprises connecting the control gates ( 14 ) to a control-gate voltage ( Vg ), connecting the sources ( 11 ) to a source voltage ( Vs ) having a higher potential than the control-gate voltage ( Vg ) and connecting the drains ( 12 ) to a drain subcircuit ( DS ) having, in at least one embodiment, a potential ( Vd ) between the control-gate voltage ( Vg ) and the source voltage ( Vs ), the drain subcircuit ( DS ) having a sufficiently low impedance to allow current flow between the sources ( 11 ) and drains ( 12 ) at a time during the erasing operation. The drain subcircuit ( DS ) allows for optimum threshold voltage distribution and a part of the drain potential ( Vd ) may be fed back to arrest the erase process at an optimum point.