公开(公告)号：EP0813239A1

公开(公告)日：1997-12-17

申请号：EP97102734.7

申请日：1997-02-20

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： Chatterjee, Amitava ,  Houston, Theodore W. ,  Chen, Ih-Chin ,  Esquirel, Agerico L. ,  Nag, Somnath ,  Ali, Iqbal ,  Joyner, Keith A. ,  Hu, Yin ,  McKee, Jeffrey A. ,  McAnally, Peter S.

IPC分类号： H01L21/762 ,  H01L21/3105

CPC分类号： H01L21/76229 ,  H01L21/31053 ,  Y10S148/05

摘要： A technique of producing a semiconductor device or integrated circuit produces a planarized refill layer which has a more uniform thickness after polishing, such as by chemical-mechanical polishing (CMP). Dummy active areas are inserted between active areas in that portion of the substrate which would normally be occupied by a field oxide in order to reduce to "dishing" that occurs during CMP in these areas. The dummy active areas can take the shape of a large block, a partially or completely formed ring structure or a plurality of pillars the area density of which can be adjusted to match the area density of the active areas in that region of the substrate. The design rule for the pillars can be such that no pillars are placed where polycrystalline silicon lines or first level metallization lines are to be placed in order to avoid parasitic capacitances.

摘要翻译： 生产半导体器件或集成电路的技术产生平坦化的填充层，其在抛光之后具有更均匀的厚度，例如通过化学机械抛光（CMP）。 虚拟有效区域插入衬底的通常会被场氧化物占据的部分中的有源区域之间，以便减少在CMP期间在这些区域发生的“凹陷”。 伪有效区域可以采取大块的形状，部分或完全形成的环形结构或多个支柱，其面积密度可被调节以匹配衬底的该区域中的有源区域的面积密度。 柱子的设计规则可以是这样的，即在多晶硅线或第一级金属化线要放置的位置不放置柱子以避免寄生电容。