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24 条记录 (耗时 0.011 秒)

    Method of manufacturing a MOSFET
    2.
    发明公开
    Method of manufacturing a MOSFET 失效
    一种用于制造MOSFET的方法

    公开(公告)号：EP0813234A3

    公开(公告)日：1999-05-26

    申请号：EP97109395.0

    申请日：1997-06-10

    申请人： TEXAS INSTRUMENTS INCORPORATED

    发明人： Hu, Jerry Che-Jen ,  Hong, Qi-Zhong ,  Hsia, Steve ,  Chen, Ih-Chin

    IPC分类号： H01L21/336 ,  H01L21/225 ,  H01L21/285

    CPC分类号： H01L29/66575 ,  H01L21/2257 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/66545

    摘要： A method for forming a ultra-shallow junction region (104). A silicon film (single crystalline, polycrystalline or amorphous) is deposited on the substrate (100) to form an elevated S/D (106). A metal film is deposited over the silicon film and reacted with the silicon film to form a silicide film (108). The silicon film is preferably completely consumed by the silicide film formation. An implant is performed to implant the desired dopant either into the metal film prior to silicide formation or into the silicide film after silicide formation. A high temperature anneal is used to drive the dopant out of the silicide film to form the junction regions (104) having a depth in the substrate (100) less than 200A. This high temperature anneal may be one of the anneals that are part of the silicide process or it may be an additional process step.

    Method of forming a trench isolation structure in an integrated circuit
    5.
    发明公开
    Method of forming a trench isolation structure in an integrated circuit 失效
    一种用于在集成电路中制备用于隔离一个严重的结构的方法

    公开(公告)号：EP0773582A3

    公开(公告)日：1999-07-14

    申请号：EP96118203.7

    申请日：1996-11-13

    申请人： TEXAS INSTRUMENTS INCORPORATED

    发明人： Chen, Ih-Chin

    IPC分类号： H01L21/762 ,  H01L21/308

    CPC分类号： H01L21/763 ,  H01L21/0337 ,  H01L21/76202 ,  H01L21/76232

    摘要： A method of making a semiconductor device or integrated circuit produces trench isolation structures having rounded corners in order to reduce gate oxide weakness and to avoid the so-called "double hump" curve produced by the corner effect. A LOCOS oxide is removed from the surface of a silicon substrate to produce a depression in the surface. A silicon dioxide or silicon nitride layer is deposited over the surface including the silicon nitride used in the LOCOS process. The surface in anisotropically etched to form sidewall spacers either side of the area where the trench is to be formed. The substrate is then etched to form a trench. In an alternative method, nitride sidewalls are formed prior to removing the LOCOS oxide. The resulting structure is anisotropically etched to leave sidewalls on either side of the trench location, the sidewalls being made of the silicon nitride sidewall and the remainder of the LOCOS oxide. The substrate would then be etched to form the trench.

    Improvements in or relating to semiconductor devices
    6.
    发明公开
    Improvements in or relating to semiconductor devices 失效
    半导体器件或与之相关的改进

    公开(公告)号：EP0813239A1

    公开(公告)日：1997-12-17

    申请号：EP97102734.7

    申请日：1997-02-20

    申请人： TEXAS INSTRUMENTS INCORPORATED

    发明人： Chatterjee, Amitava ,  Houston, Theodore W. ,  Chen, Ih-Chin ,  Esquirel, Agerico L. ,  Nag, Somnath ,  Ali, Iqbal ,  Joyner, Keith A. ,  Hu, Yin ,  McKee, Jeffrey A. ,  McAnally, Peter S.

    IPC分类号： H01L21/762 ,  H01L21/3105

    CPC分类号： H01L21/76229 ,  H01L21/31053 ,  Y10S148/05

    摘要： A technique of producing a semiconductor device or integrated circuit produces a planarized refill layer which has a more uniform thickness after polishing, such as by chemical-mechanical polishing (CMP). Dummy active areas are inserted between active areas in that portion of the substrate which would normally be occupied by a field oxide in order to reduce to "dishing" that occurs during CMP in these areas. The dummy active areas can take the shape of a large block, a partially or completely formed ring structure or a plurality of pillars the area density of which can be adjusted to match the area density of the active areas in that region of the substrate. The design rule for the pillars can be such that no pillars are placed where polycrystalline silicon lines or first level metallization lines are to be placed in order to avoid parasitic capacitances.

    摘要翻译： 生产半导体器件或集成电路的技术产生平坦化的填充层，其在抛光之后具有更均匀的厚度，例如通过化学机械抛光（CMP）。 虚拟有效区域插入衬底的通常会被场氧化物占据的部分中的有源区域之间，以便减少在CMP期间在这些区域发生的“凹陷”。 伪有效区域可以采取大块的形状，部分或完全形成的环形结构或多个支柱，其面积密度可被调节以匹配衬底的该区域中的有源区域的面积密度。 柱子的设计规则可以是这样的，即在多晶硅线或第一级金属化线要放置的位置不放置柱子以避免寄生电容。

    Method of forming a trench isolation structure in an integrated circuit
    7.
    发明公开
    Method of forming a trench isolation structure in an integrated circuit 失效
    一种用于在集成电路中制备用于隔离一个严重的结构的方法

    公开(公告)号：EP0773582A2

    公开(公告)日：1997-05-14

    申请号：EP96118203.7

    申请日：1996-11-13

    申请人： TEXAS INSTRUMENTS INCORPORATED

    发明人： Chen, Ih-Chin

    IPC分类号： H01L21/762 ,  H01L21/308

    CPC分类号： H01L21/763 ,  H01L21/0337 ,  H01L21/76202 ,  H01L21/76232

    摘要： A method of making a semiconductor device or integrated circuit produces trench isolation structures having rounded corners in order to reduce gate oxide weakness and to avoid the so-called "double hump" curve produced by the corner effect. A LOCOS oxide is removed from the surface of a silicon substrate to produce a depression in the surface. A silicon dioxide or silicon nitride layer is deposited over the surface including the silicon nitride used in the LOCOS process. The surface in anisotropically etched to form sidewall spacers either side of the area where the trench is to be formed. The substrate is then etched to form a trench. In an alternative method, nitride sidewalls are formed prior to removing the LOCOS oxide. The resulting structure is anisotropically etched to leave sidewalls on either side of the trench location, the sidewalls being made of the silicon nitride sidewall and the remainder of the LOCOS oxide. The substrate would then be etched to form the trench.

    摘要翻译： 一种制造半导体器件的方法或集成电路产生具有圆角，以减小栅极氧化物弱点，并避免由角效应产生的所谓的“双峰”曲线沟槽隔离结构。 甲LOCOS氧化从硅衬底的表面除去，以在表面的凹陷。 二氧化硅或氮化硅层沉积在表面包含在LOCOS工艺中使用的氮化硅上。 在各向异性地蚀刻所述表面以形成侧壁间隔件，其中所述沟槽将要形成的区域的任一侧上。 然后，将基片进行蚀刻以形成沟槽。 在可替换的方法中，氮化物侧壁之前去除LOCOS氧化形成。 所得到的结构是各向异性蚀刻以留下侧壁上的沟槽位置的任一侧上，所述侧壁被由氮化硅侧壁和LOCOS氧化的其余部分。 然后将基材会被蚀刻以形成沟槽。

    Improvements in or relating to dynamic random access memory devices
    8.
    发明公开
    Improvements in or relating to dynamic random access memory devices 失效
    Verbesserungen在一个动态的Speicheranordnungen mit wahlfreiem祖格里夫。

    公开(公告)号：EP0681331A2

    公开(公告)日：1995-11-08

    申请号：EP95302940.2

    申请日：1995-04-28

    申请人： TEXAS INSTRUMENTS INCORPORATED

    发明人： Chen, Ih-Chin ,  Teng, Clarence W. ,  Shichijo Hisashi.

    IPC分类号： H01L27/108 ,  H01L27/02

    CPC分类号： H01L27/10805 ,  H01L27/105

    摘要： A dynamic random access memory device (10) includes three separate sections - an input/output section (12), a peripheral transistor section (14), and a memory array section (16), all formed on a p- type substrate layer (18). The dynamic random access memory device (10) can employ separate substrate bias voltages for each section. The input/output section (12) has a p- type region (22) that is isolated from the p- type substrate layer (18) by an n- type well region (20). The peripheral transistor section (14) has a p- type region (36) that can be isolated from the p- type substrate layer (18) by an optional n- type well region (40) for those devices which require a different substrate bias voltage between the peripheral transistor section (14) and the memory array section (16).

    摘要翻译： 动态随机存取存储器件（10）包括三个单独的部分 - 输入/输出部分（12），外围晶体管部分（14）和存储器阵列部分（16），全部形成在p型衬底层 18）。 动态随机存取存储器件（10）可以为每个部分采用单独的衬底偏置电压。 输入/输出部分（12）具有通过n-型阱区域（20）与p-型衬底层（18）隔离的p-型区域（22）。 外围晶体管部分（14）具有p型区域（36），其可以通过可选的n型阱区域（40）与p型衬底层（18）隔离，用于需要不同衬底偏置的器件 外围晶体管部分（14）和存储器阵列部分（16）之间的电压。

    Improvements relating to semiconductor devices
    10.
    发明公开
    Improvements relating to semiconductor devices 失效
    在Zusammenhang mit Halbleitervorrichtungen的Verbesserungen

    公开(公告)号：EP2287901A2

    公开(公告)日：2011-02-23

    申请号：EP10186092.2

    申请日：1997-06-09

    申请人： Texas Instruments Incorporated

    发明人： Nag, Somnath S. ,  Chatterjee, Amitava ,  Chen, Ih-Chin

    IPC分类号： H01L21/762

    CPC分类号： H01L21/76229 ,  H01L21/76224 ,  Y10S148/05

    摘要： A trench isolation structure including growing a layer of thermal oxide (114) on the silicon exposed in the trenches (110) prior to depositing the layer of insulating material, wherein the layer of thermal oxide (114) forms a lining on the trench. Depositing the layer of insulating material (120) comprises depositing a silicon oxide with an inductively-coupled high density plasma, wherein the plasma bias of the high density plasma is ramped from a low bias to a high bias

    摘要翻译： 一种沟槽隔离结构，包括在沉积绝缘材料层之前，在暴露在沟槽（110）中的硅上生长一层热氧化物（114），其中该热氧化层（114）在该沟槽上形成衬里。 沉积绝缘材料层（120）包括用感应耦合的高密度等离子体沉积氧化硅，其中高密度等离子体的等离子体偏压从低偏压斜升到高偏压