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    CHROMINANCE PROCESSING SYSTEM
    2.
    发明授权
    CHROMINANCE PROCESSING SYSTEM 失效
    铬染料加工系统

    公开(公告)号：EP0532635B1

    公开(公告)日：1997-08-06

    申请号：EP91911305.0

    申请日：1991-05-30

    申请人： THOMSON CONSUMER ELECTRONICS, INC.

    发明人： ERSOZ, Nathanial, Haluk ,  SAEGER, Timothy, William ,  DOTY, James, Harrison, II ,  KRANAWETTER, Greg, Alan

    IPC分类号： H04N11/06 ,  H04N7/04

    CPC分类号： H04N9/641 ,  G06T3/0012 ,  G06T3/4007 ,  H04N3/223 ,  H04N3/227 ,  H04N3/27 ,  H04N5/2624 ,  H04N5/45 ,  H04N7/007 ,  H04N7/01 ,  H04N7/0105 ,  H04N7/0122 ,  H04N7/015 ,  H04N9/64 ,  H04N19/90

    摘要： Video luminance data from a video signal is selectably compressed and expanded in a first signal path including a first line memory (356). A second line memory (358) in a parallel signal path processes video chrominance data from the video signal. A control circuit (320) generates respective timing signals for writing data into the line memories and for reading data from the line memories. A timing delay circuit (337) for the control means, has video compression and expansion modes of operation. During the compression mode, reading of the second line memory is delayed relative to writing of the second line memory. During said expansion mode, writing of the first line memory is delayed relative to writing of the second line memory or reading of the second line memory is delayed relative to writing of the second line memory. The duration of the timing delays can be selected from a range of values. The line memories are first in first out (FIFO) devices having independently enabled write and read ports.

    摘要翻译： 来自视频信号的视频亮度数据在包括第一行存储器（356）的第一信号路径中被选择性地压缩和扩展。 并行信号路径中的第二行存储器（358）处理来自视频信号的视频色度数据。 控制电路（320）产生用于将数据写入行存储器和从行存储器读取数据的各个定时信号。 用于控制装置的定时延迟电路（337）具有视频压缩和扩展操作模式。 在压缩模式期间，第二行存储器的读取相对于第二行存储器的写入被延迟。 在所述扩展模式期间，第一行存储器的写入相对于第二行存储器的写入被延迟，或者第二行存储器的读取相对于第二行存储器的写入被延迟。 定时延迟的持续时间可以从一系列值中选择。 行存储器是具有独立使能的写入和读取端口的先进先出（FIFO）设备。