公开(公告)号：EP0810646A2

公开(公告)日：1997-12-03

申请号：EP97105449.9

申请日：1997-04-02

申请人： TRW INC.

发明人： Oki, Aaron Kenji ,  Streit, Dwight Christopher ,  Umemoto, Donald Katsu ,  Tran, Liem T.

IPC分类号： H01L21/331 ,  H01L29/737

CPC分类号： H01L29/66318 ,  H01L29/7371

摘要： A heterojunction bipolar transistor with a vertically integrated profile includes a substrate layer, a collector contact layer, a collector layer, a base layer and an emitter layer, formed from AlGaAs, etched to form an emitter mesa leaving a relatively thin passivating layer, adjacent the emitter mesa. The base metal contacts are formed on the passivating layer, resulting in a wider bandgap, thus minimizing surface recombination velocity at the emitter-base junction and increasing the overall gain (β) of the device. The base metal contacts are formed by evaporating a p-ohmic metal onto the n-type passivation layer. The p-ohmic contacts are annealed, resulting in p-type metal diffusion through the passivating layer and reaction with the base layer, resulting in ohmic contacts.

摘要翻译： 具有垂直集成形状的异质结双极晶体管包括由AlGaAs形成的衬底层，集电极接触层，集电极层，基极层和发射极层，被蚀刻以形成离开较薄钝化层的发射极台面，邻近 发射台台面 贱金属触点形成在钝化层上，导致更宽的带隙，从而最小化发射极 - 基极结处的表面复合速度并增加器件的总增益（β）。 通过将p-欧姆金属蒸发到n型钝化层上来形成基底金属触点。 p欧姆接触被退火，导致p型金属通过钝化层扩散并与基层反应，导致欧姆接触。

公开(公告)号：EP0541205A3

公开(公告)日：1993-07-14

申请号：EP92305677.4

申请日：1992-06-19

申请人： TRW INC.

发明人： Streit, Dwight Christopher ,  Oki, Aaron Kenji ,  Umemoto, Donald K. ,  Velebir, James Russell, Jr.

IPC分类号： H01L21/82 ,  H01L27/082

CPC分类号： H01L21/8252 ,  H01L27/0605 ,  H01L27/0826 ,  Y10S148/072

摘要： Disclosed is a method for fabricating complementary heterojunction bipolar transistors on a common substrate. The method comprises the steps of depositing a PNP profile (14) by molecular beam epitaxy on an appropriate substrate (12) and then depositing a layer of silicon nitride (16) on the PNP profile just deposited. The substrate is then heated in a vacuum in order to densify the silicon nitride. A mask (20) and resist layer (18) are used to produce the desired PNP profile patterns. The NPN profile (22) is deposited on the area of the substrate (12) etched away as well as on the silicon nitride layer (16) protecting the already deposited PNP layers. The NPN profile (22) is then patterned using a resist (24) and masking process. The polycrystalline NPN area on top of the silicon nitride layer and the remaining silicon nitride layer are etched away forming two adjacent complementary NPN and PNP profiles on a common substrate. In the fabrication of the heterojunction bipolar transistor circuits, the P-ohmic contacts on both the NPN and PNP materials is evaporated at the appropriate locations simultaneously. All of the N-ohmic contacts are also deposited simultaneously. By this, the complementary dual heterojunction bipolar transistor device can be effectively fabricated with excellent DC and microwave capabilities.

公开(公告)号：EP0810644A3

公开(公告)日：1998-01-28

申请号：EP97105382.2

申请日：1997-04-01

申请人： TRW INC.

发明人： Oki, Aaron Kenji ,  Umemoto, Donald Katsu ,  Tran, Liem T. ,  Streit, Dwight Christopher

IPC分类号： H01L21/329 ,  H01L29/872

CPC分类号： H01L29/66212 ,  H01L29/872

摘要： A Schottky barrier diode and a method for fabricating a Schottky barrier diode that utilizes HBT active device layers. The Schottky barrier diode is formed with a vertically integrated profile on a GaAs substrate, with a subcollector layer and a collector layer. A suitable dielectric material is deposited on top of the collector layer. Vias are formed in the collector layer and subcollector layer for the barrier and ohmic contacts. The collector via is relatively deeply etched into the collector layer to lower the series resistance between the barrier and ohmic contacts, which results in relatively higher cut-off frequency performance.

公开(公告)号：EP0810644A2

公开(公告)日：1997-12-03

申请号：EP97105382.2

申请日：1997-04-01

申请人： TRW INC.

发明人： Oki, Aaron Kenji ,  Umemoto, Donald Katsu ,  Tran, Liem T. ,  Streit, Dwight Christopher

IPC分类号： H01L21/329 ,  H01L29/872

CPC分类号： H01L29/66212 ,  H01L29/872

摘要： A Schottky barrier diode and a method for fabricating a Schottky barrier diode that utilizes HBT active device layers. The Schottky barrier diode is formed with a vertically integrated profile on a GaAs substrate, with a subcollector layer and a collector layer. A suitable dielectric material is deposited on top of the collector layer. Vias are formed in the collector layer and subcollector layer for the barrier and ohmic contacts. The collector via is relatively deeply etched into the collector layer to lower the series resistance between the barrier and ohmic contacts, which results in relatively higher cut-off frequency performance.

摘要翻译： 一种肖特基势垒二极管和一种利用HBT有源器件层制造肖特基势垒二极管的方法。 肖特基势垒二极管在GaAs衬底上形成垂直集成的形状，具有子集电极层和集电极层。 在集电极层的顶部上沉积合适的介电材料。 在集电极层和子集电极层中形成用于屏障和欧姆接触的通孔。 集电极通孔相对深度地蚀刻到集电极层中，以降低阻挡层和欧姆接触之间的串联电阻，这导致相对较高的截止频率性能。

公开(公告)号：EP0529772A1

公开(公告)日：1993-03-03

申请号：EP92305531.3

申请日：1992-06-17

申请人： TRW INC.

发明人： Streit, Dwight Christopher ,  Oki, Aaron Kenji

IPC分类号： H01L21/331 ,  H01L21/203 ,  H01L29/73

CPC分类号： H01L29/66318 ,  H01L29/207 ,  H01L29/7371 ,  Y10S438/936

摘要： A technique for producing high reliability GaAs-AlGaAs heterojunction bipolar transistors by Molecular Beam Epitaxy with beryllium base doping. Beryllium incorporation and diffusion, during base-layer deposition, is controlled through a combination of reduced substrate temperature and increase As/Ga flux ratio during MBE growth resulting in extremely stable heterojunction bipolar transistor profiles. In addition, graded InGaAs surface layers with non-alloyed refractory metal contacts are shown to significantly improve ohmic reliability to alloyed AuGe contacts. High gain (DC beta) is achieved by the use of an increased substrate temperature during emitter deposition. The HBTs in accordance with the present invention are useful in a number of important microwave applications such as log amps, a/d converters, and sample and hold circuits where high reliability is desired.

摘要翻译： 通过分子束外延生产具有铍基底掺杂的高可靠性GaAs-AlGaAs异质结双极晶体管的技术。 在基层沉积期间，通过降低衬底温度和在MBE生长期间增加As / Ga通量比的组合来控制铍的掺入和扩散，从而产生非常稳定的异质结双极晶体管轮廓。 此外，显示出具有非合金化难熔金属触点的分级InGaAs表面层显着提高合金AuGe触点的欧姆可靠性。 通过在发射极沉积期间使用增加的衬底温度来实现高增益（DCβ）。 根据本发明的HBT可用于许多重要的微波应用，例如对数放大器，a / d转换器以及需要高可靠性的采样和保持电路。

公开(公告)号：EP1134809A2

公开(公告)日：2001-09-19

申请号：EP01106729.5

申请日：2001-03-16

申请人： TRW Inc.

发明人： Gutierrez-Aitken, Augusto L. ,  Oki, Aaron Kenji ,  Kaneshiro, Eric N. ,  Streit, Dwight Christopher

IPC分类号： H01L29/737 ,  H01L29/10 ,  H01L21/331

CPC分类号： H01L29/66318 ,  H01L29/045 ,  H01L29/1004 ,  H01L29/7371

摘要： Reduction in the base to collector capacitance of a heterojunction bipolar transistor, and, improved high frequency performance is achieved using existing materials and processes by undercutting the collector (5)under the base (7) along two parallel sides of the base mesa (7 - Fig. 4), and providing a sloped collector edge (5-Fig. 6) along the remaining two parallel sides of the base. The foregoing is accomplished by selective etching and with the four sides of the mesa regions oriented as a non-rectangular parallelogram (7, 9 - Fig. 4) in which one pair of sides is in parallel with one of the said [0 0 1] and [0 0 1 ¯ ] planes of the crystalline structure and the other pair of sides in parallel with one of the [0 1 1] and [0 1 1 ¯ ] planes of the crystalline structure.

摘要翻译： 通过使用现有的材料和工艺，通过在基底（7）下方的底部（7）的底部（7）的两个平行的侧面下切割来实现异质结双极晶体管的基极到集电极电容的降低，以及改进的高频性能， 图4），并且沿着底座的剩余的两个平行侧提供倾斜的收集器边缘（图5-图6）。 前述是通过选择性蚀刻实现的，并且台面区域的四个侧面被定向为非矩形平行四边形（7,9-图4），其中一对侧面与所述Ä00 1Ü和 晶体结构的平面和另一对边缘平行于晶体结构的一个Ä01 1Ü平面和Ä011 1平面。

公开(公告)号：EP0794613B1

公开(公告)日：2001-08-16

申请号：EP97100525.1

申请日：1997-01-15

申请人： TRW INC.

发明人： Kobayashi, Kevin Wesley ,  Streit, Dwight Christopher ,  Oki, Aaron Kenji ,  Umemoto, Donald Katsu

IPC分类号： H03F3/193

CPC分类号： H03F3/211 ,  H03F1/32 ,  H03F3/1935 ,  H03F3/3455 ,  H03F2200/294 ,  H03F2200/372

公开(公告)号：EP0810646A3

公开(公告)日：1998-01-14

申请号：EP97105449.9

申请日：1997-04-02

申请人： TRW INC.

发明人： Oki, Aaron Kenji ,  Streit, Dwight Christopher ,  Umemoto, Donald Katsu ,  Tran, Liem T.

IPC分类号： H01L21/331 ,  H01L29/737

CPC分类号： H01L29/66318 ,  H01L29/7371

摘要： A heterojunction bipolar transistor with a vertically integrated profile includes a substrate layer, a collector contact layer, a collector layer, a base layer and an emitter layer, formed from AlGaAs, etched to form an emitter mesa leaving a relatively thin passivating layer, adjacent the emitter mesa. The base metal contacts are formed on the passivating layer, resulting in a wider bandgap, thus minimizing surface recombination velocity at the emitter-base junction and increasing the overall gain (β) of the device. The base metal contacts are formed by evaporating a p-ohmic metal onto the n-type passivation layer. The p-ohmic contacts are annealed, resulting in p-type metal diffusion through the passivating layer and reaction with the base layer, resulting in ohmic contacts.

摘要翻译： 具有垂直集成轮廓的异质结双极晶体管包括由AlGaAs形成的衬底层，集电极接触层，集电极层，基极层和发射极层，刻蚀以形成发射极台面，留下相对薄的钝化层，邻近 发射极台面。 贱金属触点形成在钝化层上，导致更宽的带隙，从而使发射极 - 基极结处的表面复合速度最小化并且增加器件的总体增益（β）。 通过将p-欧姆金属蒸发到n型钝化层上来形成贱金属触点。 p-欧姆接触被退火，导致p型金属扩散穿过钝化层并与基层反应，导致欧姆接触。

公开(公告)号：EP0810645A2

公开(公告)日：1997-12-03

申请号：EP97105251.9

申请日：1997-03-27

申请人： TRW INC.

发明人： Oki, Aaron Kenji ,  Umemoto, Donald Katsu ,  Tran, Liem T. ,  Streit, Dwight Christopher

IPC分类号： H01L21/331 ,  H01L29/737

CPC分类号： H01L29/66318 ,  Y10S148/01 ,  Y10S148/011 ,  Y10S148/072 ,  Y10S148/10 ,  Y10S148/143

摘要： A heterojunction bipolar transistor and a method for fabricating an HBT with self-aligned base metal contacts using a double photoresist, which requires fewer process steps than known methods, while minimizing damage to the active emitter contact region. In particular, a photoresist is used to form the emitter mesa. The emitter mesa photoresist is left on and a double polymethylmethacrylate (PMMA) and photoresist layer is then applied. The triple photoresist combination is patterned to create a non-critical lateral alignment for the base metal contacts to the emitter mesa, which permits selective base ohmic metal deposition and lift-off. By utilizing the double photoresist as opposed to a metal or dielectric for masking, an additional photolithography step and etching step is eliminated. By eliminating the need for an additional etching step, active regions of the semiconductors are prevented from being exposed to the etching step and possibly damaged.

摘要翻译： 异相结双极晶体管和使用双光致抗蚀剂制造具有自对准基底金属触点的HBT的方法，其比已知方法需要更少的工艺步骤，同时最小化对有源发射极接触区域的损害。 特别地，光致抗蚀剂用于形成发射极台面。 留下发射台面光致抗蚀剂，然后施加双重聚甲基丙烯酸甲酯（PMMA）和光致抗蚀剂层。 图案化三光致抗蚀剂组合以产生用于基底金属接触到发射极台面的非关键侧向对准，这允许选择性基极欧姆金属沉积和剥离。 通过利用双光致抗蚀剂与用于掩蔽的金属或电介质相反，消除了额外的光刻步骤和蚀刻步骤。 通过消除对另外的蚀刻步骤的需要，可以防止半导体的有源区暴露于蚀刻步骤并且可能被损坏。

公开(公告)号：EP0794613A1

公开(公告)日：1997-09-10

申请号：EP97100525.1

申请日：1997-01-15

申请人： TRW INC.

发明人： Kobayashi, Kevin Wesley ,  Streit, Dwight Christopher ,  Oki, Aaron Kenji ,  Umemoto, Donald Katsu

IPC分类号： H03F3/193

CPC分类号： H03F3/211 ,  H03F1/32 ,  H03F3/1935 ,  H03F3/3455 ,  H03F2200/294 ,  H03F2200/372

摘要： 4-terminal HEMT-HBT composite devices, based upon monolithically integrated HEMT-HBT technology and configured in various topologies, are useful in a wide range of applications which currently utilize discrete MMICs. In particular, the 4-terminal topologies are easily configured as 3-terminal composite devices useful in various 2-port and 3-port MMIC circuit applications, such as low noise-high linearity amplifiers as well as mixers, which provide the benefits of a reduction in size, as well as corresponding cost while providing better performance than utilizing either HEMT or HBT devices individually.

摘要翻译： 基于单片集成HEMT-HBT技术并配置在各种拓扑中的4端子HEMT-HBT复合器件在目前使用分立MMIC的广泛应用中非常有用。 特别地，4端子拓扑结构容易配置为可用于各种2端口和3端口MMIC电路应用中的3端复合器件，例如低噪声高线性放大器以及混频器，其提供了一个 减小尺寸，以及相应的成本，同时提供比单独使用HEMT或HBT设备更好的性能。