公开(公告)号：EP1495538A1

公开(公告)日：2005-01-12

申请号：EP03746961.6

申请日：2003-04-11

申请人： Thomson Licensing S.A. ,  Markman, Ivonete

发明人： MARKMAN, Ivonete ,  PARK, Jeongsoon ,  HEO, Seo, Weon ,  GELFAND, Saul, Brian

IPC分类号： H03H7/40

CPC分类号： H04L25/03057 ,  H04L2025/0349 ,  H04L2025/037 ,  H04L2025/03732 ,  H04N5/211

摘要： An apparatus for automatically selecting one of a standard decision directed (dd) mode and a soft dd mode in a decision feedback equalizer (DFE) for receiving a data signal comprises an equalizer for providing a DFE output signal and having a control input responsive to a control signal exhibiting a first value for selecting the standard dd mode and a second value for selecting the soft dd mode. The equalizer includes a lock detector (20) having an output for providing a lock signal indicative of equalizer convergence. The apparatus includes a mode selector (18) having an input coupled to the lock detector (20) output and having an output coupled to the control input for providing an output signal exhibiting one of the first and second values depending upon characteristics of the lock signal.

公开(公告)号：EP1497916A1

公开(公告)日：2005-01-19

申请号：EP03746957.4

申请日：2003-04-09

申请人： Thomson Licensing S.A.

发明人： HEO, Seo, Weon ,  MARKMAN, Ivonete ,  PARK, Jeongsoon ,  GELFAND, Saul, Brian

IPC分类号： H03H7/30

CPC分类号： H04N5/211 ,  H04L25/03038 ,  H04L25/03057 ,  H04L25/067 ,  H04L2025/0349 ,  H04L2025/037 ,  H04L2025/03732

摘要： A decision feedback equalizer for processing a data signal provides concurrent equalizer outputs (Zok, Z1k) for hard decision directed and soft decision directed modes. The joint architecture in accordance with the present invention takes advantage of the fact, herein recognized, that for each equalizer output symbol soft decision bit representation, a subset of these bits corresponds to the hard decision representation. As a result, the invention permits the concurrent output of two distinct modes with essentially the same hardware as a one output equalizer.

摘要翻译： 用于处理数据信号的判定反馈均衡器为硬判定导向模式和软判决导向模式提供并发均衡器输出（Zok，Z1k）。 根据本发明的联合体系结构利用了这里认识到的事实，即对于每个均衡器输出码元软判决比特表示，这些比特的子集对应于硬判决表示。 结果，本发明允许具有与一个输出均衡器基本相同的硬件的两个不同模式的并发输出。

公开(公告)号：EP1495608A2

公开(公告)日：2005-01-12

申请号：EP03721592.8

申请日：2003-04-09

申请人： Thomson Licensing S.A. ,  Heo, Seo Weon

发明人： HEO, Seo, Weon ,  PARK, Jeongsoon ,  GELFAND, Saul, Brian ,  MARKMAN, Ivonete

IPC分类号： H04L27/01 ,  H04L27/06 ,  H04N7/66 ,  H04N11/24

CPC分类号： H04N21/4382 ,  H03M13/256 ,  H03M13/3746 ,  H03M13/6331 ,  H04L1/0055 ,  H04L1/006 ,  H04L1/208 ,  H04L25/03057 ,  H04L2025/03382 ,  H04L2025/0349 ,  H04L2025/037 ,  H04L2025/03732 ,  H04N5/211 ,  H04N5/4401

摘要： A concatenated equalizer/trellis decoding system for use in processing a High Definition Television signal. The re-encoded trellis decoder output, rather than the equalizer output, is used as an input to the feedback filter of the decision feedback equalizer. Hard or soft decision trellis decoding may be applied. In order to account for the latency associated with trellis decoding and the presence of twelve interleaved decoders, feedback from the trellis decoder to the equalizer is performed by replicating the trellis decoder and equalizer hardware in a module that can be cascaded in as many stages as needed to achieve the desired balance between complexity and performance. The present system offers an improvement of between 0.6 and 1.9 decibels. Cascading of two modules is usually sufficient to achieve most of the potential performance improvement.

公开(公告)号：EP1495564A1

公开(公告)日：2005-01-12

申请号：EP03723986.0

申请日：2003-04-10

申请人： Thomson Licensing S.A.

发明人： PARK, Jeongsoon ,  HEO, Seo, Weon ,  MARKMAN, Ivonete ,  GELFAND, Saul, Brian

IPC分类号： H04J3/12 ,  H04N7/10 ,  H03H15/00 ,  G06F11/10

CPC分类号： H04N5/211 ,  H04L1/0046 ,  H04L1/005 ,  H04L1/20 ,  H04L25/03057 ,  H04L2025/0349 ,  H04L2025/037 ,  H04L2025/03732 ,  H04N7/102

摘要： An apparatus for automatically selecting one of a standard decision directed (dd) mode and a soft dd mode in a decision feedback equalizer (DFE) for receiving a data signal includes an equalizer (30) utilizing forward error correction (FEC) for providing first and second output signals corresponding to a DFE automatic switching mode and a soft automatic switching mode, respectively, and a comparator (36) for comparing byte error rates (ByER) of the first and second output signals for selecting as a superior mode that mode associated with a lower ByER and outputting the output signal with the lower ByER. A lock detector (30) provides a lock signal derived from the DFE output signal with the lower ByER and a mode switch (38) selectively places the DFE outputs in one of the dd modes or a blind mode, depending on the lock signal.