公开(公告)号：EP4236665A2

公开(公告)日：2023-08-30

申请号：EP23180030.1

申请日：2020-11-25

申请人： United Microelectronics Corp.

发明人： WANG, Hui-Lin ,  HSU, Po-Kai ,  FAN, Ju-Chun ,  LIN, Yi-Yu ,  HSU, Ching-Hua ,  CHEN, Hung-Yueh

IPC分类号： H10N59/00

摘要： A semiconductor device, comprising: a substrate; a first dielectric layer disposed on the substrate, the first dielectric layer around a first metal interconnection; a second dielectric layer disposed on the first dielectric layer, the second dielectric layer around a via and a second metal interconnection, the second metal interconnection directly contacting the first metal interconnection; and a third dielectric layer disposed on the second dielectric layer, the third dielectric layer around a first magnetic tunneling junction, MTJ, structure and a third metal interconnection, wherein the third metal interconnection directly contacts top surfaces of the first MTJ structure and the second metal interconnection, and the first MTJ structure directly contacts the via.

公开(公告)号：EP3985749A1

公开(公告)日：2022-04-20

申请号：EP20209712.7

申请日：2020-11-25

申请人： United Microelectronics Corp.

发明人： WANG, Hui-Lin ,  HSU, Po-Kai ,  FAN, Ju-Chun ,  LIN, Yi-Yu ,  HSU, Ching-Hua ,  CHEN, Hung-Yueh

IPC分类号： H01L43/08 ,  H01L27/22 ,  G11C11/16 ,  G11C11/15

摘要： A semiconductor device includes a substrate, a first dielectric layer, a second dielectric layer, and a third dielectric layer. The first dielectric layer is disposed on the substrate, around a first metal interconnection. The second dielectric layer is disposed on the first dielectric layer, around a via and a second metal interconnection. The second metal interconnection directly contacts the first metal interconnection. The third dielectric layer is disposed on the second dielectric layer, around a first magnetic tunneling junction (MTJ) structure and a third metal interconnection. The third metal interconnection directly contacts the first MTJ structure and the second metal interconnection, and the first MTJ structure directly contacts the via.

公开(公告)号：EP4447051A2

公开(公告)日：2024-10-16

申请号：EP24196552.4

申请日：2022-07-25

申请人： United Microelectronics Corp.

发明人： LIN, Yi-Yu ,  HSU, Po-Kai ,  CHIU, Chung-Yi

IPC分类号： G11C11/16

摘要： A resistive random access memory structure, comprising: a substrate; a transistor disposed on the substrate, wherein the transistor comprises a gate structure, a source and a drain; a single drain contact plug having an end contacting the drain; a metal interlayer dielectric layer disposed on the drain contact plug; a resistive random access memory, RRAM, disposed on the drain and within a first trench in the metal interlayer dielectric layer, wherein the RRAM comprises the drain contact plug, a metal oxide layer and a top electrode, the drain contact plug serves as a bottom electrode of the RRAM, the metal oxide layer directly contacts another end of the single drain contact plug and the top electrode contacts the metal oxide layer; and a metal layer disposed within the first trench; the resistive random access memory structure further comprising: a second trench disposed within the metal interlayer dielectric layer, a source contact plug contacting the source and being exposed from the second trench, a buffer layer and the metal layer disposed within the second trench, and the buffer layer contacting the source contact plug.

公开(公告)号：EP4175439A1

公开(公告)日：2023-05-03

申请号：EP22186719.5

申请日：2022-07-25

申请人： United Microelectronics Corp.

发明人： LIN, Yi-Yu ,  HSU, Po-Kai ,  CHIU, Chung-Yi

IPC分类号： H10B63/00 ,  H10N70/00 ,  G11C11/16

摘要： A resistive random access memory (RRAM) structure includes a substrate. A transistor is disposed on the substrate. The transistor includes a gate structure, a source and a drain. A drain contact plug contacts the drain. A metal interlayer dielectric layer is disposed on the drain contact plug. An RRAM is disposed on the drain and within a first trench in the metal interlayer dielectric layer. The RRAM includes the drain contact plug, a metal oxide layer and a top electrode. The drain contact plug serves as a bottom electrode of the RRAM. The metal oxide layer contacts the drain contact plug. The top electrode contacts the metal oxide layer and a metal layer is disposed within the first trench.

公开(公告)号：EP4236665A3

公开(公告)日：2023-11-01

申请号：EP23180030.1

申请日：2020-11-25

申请人： United Microelectronics Corp.

发明人： WANG, Hui-Lin ,  HSU, Po-Kai ,  FAN, Ju-Chun ,  LIN, Yi-Yu ,  HSU, Ching-Hua ,  CHEN, Hung-Yueh

IPC分类号： G11C11/16 ,  H10B61/00 ,  H10N50/10

摘要： A semiconductor device, comprising: a substrate; a first dielectric layer disposed on the substrate, the first dielectric layer around a first metal interconnection; a second dielectric layer disposed on the first dielectric layer, the second dielectric layer around a via and a second metal interconnection, the second metal interconnection directly contacting the first metal interconnection; and a third dielectric layer disposed on the second dielectric layer, the third dielectric layer around a first magnetic tunneling junction, MTJ, structure and a third metal interconnection, wherein the third metal interconnection directly contacts top surfaces of the first MTJ structure and the second metal interconnection, and the first MTJ structure directly contacts the via.