利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

10 条记录 (耗时 0.011 秒)

    SEMICONDUCTOR DEVICE
    1.
    发明公开
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：EP4236665A3

    公开(公告)日：2023-11-01

    申请号：EP23180030.1

    申请日：2020-11-25

    申请人： United Microelectronics Corp.

    发明人： WANG, Hui-Lin ,  HSU, Po-Kai ,  FAN, Ju-Chun ,  LIN, Yi-Yu ,  HSU, Ching-Hua ,  CHEN, Hung-Yueh

    IPC分类号： G11C11/16 ,  H10B61/00 ,  H10N50/10

    摘要： A semiconductor device, comprising: a substrate; a first dielectric layer disposed on the substrate, the first dielectric layer around a first metal interconnection; a second dielectric layer disposed on the first dielectric layer, the second dielectric layer around a via and a second metal interconnection, the second metal interconnection directly contacting the first metal interconnection; and a third dielectric layer disposed on the second dielectric layer, the third dielectric layer around a first magnetic tunneling junction, MTJ, structure and a third metal interconnection, wherein the third metal interconnection directly contacts top surfaces of the first MTJ structure and the second metal interconnection, and the first MTJ structure directly contacts the via.

    LAYOUT PATTERN FOR MAGNETORESISTIVE RANDOM ACCESS MEMORY
    6.
    发明公开
    LAYOUT PATTERN FOR MAGNETORESISTIVE RANDOM ACCESS MEMORY 审中-公开

    公开(公告)号：EP3852161A1

    公开(公告)日：2021-07-21

    申请号：EP20174591.6

    申请日：2020-05-14

    申请人： United Microelectronics Corp.

    发明人： TSAI, Ya-Huei ,  HUANG, Rai-Min ,  WANG, Yu-Ping ,  CHEN, Hung-Yueh

    IPC分类号： H01L43/08 ,  G11C11/16 ,  H01L27/22

    摘要： A layout pattern for magnetoresistive random access memory (MRAM) includes a substrate having a first active region, a second active region, and a word line connecting region between the first active region and the second active region and a gate pattern extending from the first active region to the second active region, in which the gate pattern includes a H-shape according to a top view. Preferably, the gate pattern includes a first gate pattern extending along a first direction from the first active region to the second active region, a second gate pattern extending along the first direction from the first active region to the second active region, and a third gate pattern connecting the first gate pattern and the second gate pattern along a second direction.

    MAGNETIC MEMORY CELL AND FABRICATION METHOD THEREOF
    7.
    发明公开
    MAGNETIC MEMORY CELL AND FABRICATION METHOD THEREOF 审中-公开

    公开(公告)号：EP3767676A1

    公开(公告)日：2021-01-20

    申请号：EP20169305.8

    申请日：2020-04-14

    申请人： United Microelectronics Corp.

    发明人： HUANG, Rai-Min ,  CHEN, Hung-Yueh ,  TSAI, Ya-Huei ,  WANG, Yu-Ping

    IPC分类号： H01L27/22

    摘要： A magnetic memory cell (100) includes a substrate (10) having a memory region (MA), a transistor (200) within the memory region, a first dielectric layer (310) disposed on the substrate, a landing pad (MP) in the first dielectric layer, a second dielectric layer (320) covering the first dielectric layer and the landing pad, a cylindrical memory stack (MS) in the second dielectric layer, and a source line (SL) in the first dielectric layer. The first dielectric layer covers the memory region and the transistor. The landing pad is situated in a first horizontal plane and is coupled to a drain region (202) of the transistor. The cylindrical memory stack has a bottom electrode (BE) connected to the landing pad and a top electrode (TE) electrically connected to a bit line (BL). The source line is situated in a second horizontal plane and is connected to a source region (203)of the transistor. The second horizontal plane is lower than the first horizontal plane.

    SEMICONDUCTOR DEVICE
    8.
    发明公开
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：EP4236665A2

    公开(公告)日：2023-08-30

    申请号：EP23180030.1

    申请日：2020-11-25

    申请人： United Microelectronics Corp.

    发明人： WANG, Hui-Lin ,  HSU, Po-Kai ,  FAN, Ju-Chun ,  LIN, Yi-Yu ,  HSU, Ching-Hua ,  CHEN, Hung-Yueh

    IPC分类号： H10N59/00

    摘要： A semiconductor device, comprising: a substrate; a first dielectric layer disposed on the substrate, the first dielectric layer around a first metal interconnection; a second dielectric layer disposed on the first dielectric layer, the second dielectric layer around a via and a second metal interconnection, the second metal interconnection directly contacting the first metal interconnection; and a third dielectric layer disposed on the second dielectric layer, the third dielectric layer around a first magnetic tunneling junction, MTJ, structure and a third metal interconnection, wherein the third metal interconnection directly contacts top surfaces of the first MTJ structure and the second metal interconnection, and the first MTJ structure directly contacts the via.

    SEMICONDUCTOR DEVICE
    9.
    发明公开
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：EP3985749A1

    公开(公告)日：2022-04-20

    申请号：EP20209712.7

    申请日：2020-11-25

    申请人： United Microelectronics Corp.

    发明人： WANG, Hui-Lin ,  HSU, Po-Kai ,  FAN, Ju-Chun ,  LIN, Yi-Yu ,  HSU, Ching-Hua ,  CHEN, Hung-Yueh

    IPC分类号： H01L43/08 ,  H01L27/22 ,  G11C11/16 ,  G11C11/15

    摘要： A semiconductor device includes a substrate, a first dielectric layer, a second dielectric layer, and a third dielectric layer. The first dielectric layer is disposed on the substrate, around a first metal interconnection. The second dielectric layer is disposed on the first dielectric layer, around a via and a second metal interconnection. The second metal interconnection directly contacts the first metal interconnection. The third dielectric layer is disposed on the second dielectric layer, around a first magnetic tunneling junction (MTJ) structure and a third metal interconnection. The third metal interconnection directly contacts the first MTJ structure and the second metal interconnection, and the first MTJ structure directly contacts the via.