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1.发明公开MECHANISM TO PRECLUDE I/O-DEPENDENT LOAD REPLAYS IN OUT-OF-ORDER PROCESSOR 审中-公开机制，撤除I / O依赖LAST REPRODUCTIONS在处理器中的服务
公开(公告)号：EP3049956A1
公开(公告)日：2016-08-03
申请号：EP14891599.4
申请日：2014-12-14
发明人： COL, Gerard, M. , EDDY, Colin , HENRY, G., Glenn
IPC分类号： G06F15/163
CPC分类号： G06F9/226 , G06F1/3243 , G06F9/30043 , G06F9/3836 , G06F12/0875 , G06F2212/452
摘要： An apparatus includes first and second reservation stations. The first reservation station (421.L) dispatches a load micro instruction, and indicates on a hold bus (444) if the load micro instruction is a specified load micro instruction directed to retrieve an operand from a prescribed resource other than on-core cache memory. The second reservation station (421.1-421.N) is coupled to the hold bus (444), and dispatches one or more younger micro instructions therein that depend on the load micro instruction for execution after a number of clock cycles following dispatch of the first load micro instruction, and if it is indicated on the hold bus (444) that the load micro instruction is the specified load micro instruction, the second reservation station (421.1-421.N) is configured to stall dispatch of the one or more younger micro instructions until the load micro instruction has retrieved the operand. The resources include an input/output (I/O) unit, configured to perform I/O operations via an I/O bus coupling an out-of-order processor to I/O resources.
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公开(公告)号：EP3055768B1
公开(公告)日：2018-10-31
申请号：EP14891600.0
申请日：2014-12-14
发明人： COL, Gerard, M. , EDDY, Colin , HENRY, G., Glenn
CPC分类号： G06F9/3838 , G06F9/30043 , G06F9/3824 , G06F9/3834 , G06F9/3836 , G06F9/3855 , G06F9/3861
摘要： An apparatus including first and second reservation stations. The first reservation station dispatches a load micro instruction, and indicates on a hold bus if the load micro instruction is a specified load micro instruction directed to retrieve an operand from a prescribed resource other than on-core cache memory. The second reservation station is coupled to the hold bus, and dispatches one or more younger micro instructions therein that depend on the load micro instruction for execution after a number of clock cycles following dispatch of the first load micro instruction, and if it is indicated on the hold bus that the load micro instruction is the specified load micro instruction, the second reservation station is configured to stall dispatch of the one or more younger micro instructions until the load micro instruction has retrieved the operand. The resources include system memory, coupled an out-of-order processor via a memory bus.
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公开(公告)号：EP3055769B1
公开(公告)日：2018-10-31
申请号：EP14891601.8
申请日：2014-12-14
发明人： COL, Gerard, M. , EDDY, Colin , HENRY, G., Glenn
IPC分类号： G06F9/38
CPC分类号： G06F9/3855 , G06F1/3228 , G06F1/3296 , G06F9/30043 , G06F9/30101 , G06F9/38 , G06F9/3824 , G06F9/3836 , G06F9/384 , G06F9/3861 , G06F12/0831 , G06F12/0875 , G06F12/1009
摘要： An apparatus including first and second reservation stations. The first reservation station dispatches a load micro instruction, and indicates on a hold bus if the load micro instruction is a specified load micro instruction directed to retrieve an operand from a prescribed resource other than on-core cache memory. The second reservation station is coupled to the hold bus, and dispatches one or more younger micro instructions therein that depend on the load micro instruction for execution after a number of clock cycles following dispatch of the first load micro instruction, and if it is indicated on the hold bus that the load micro instruction is the specified load micro instruction, the second reservation station is configured to stall dispatch of the one or more younger micro instructions until the load micro instruction has retrieved the operand. The resources include a system memory that is accessed via a memory bus, the system memory comprising one or more page tables, configured to store one or more mappings between virtual addresses and physical addresses.
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公开(公告)号：EP3049956B1
公开(公告)日：2018-10-10
申请号：EP14891599.4
申请日：2014-12-14
发明人： COL, Gerard, M. , EDDY, Colin , HENRY, G., Glenn
IPC分类号： G06F15/163
CPC分类号： G06F9/226 , G06F1/3243 , G06F9/30043 , G06F9/38 , G06F9/3836 , G06F12/0875 , G06F15/163 , G06F2212/452
摘要： An apparatus including first and second reservation stations. The first reservation station dispatches a load micro instruction, and indicates on a hold bus if the load micro instruction is a specified load micro instruction directed to retrieve an operand from a prescribed resource other than on-core cache memory. The second reservation station is coupled to the hold bus, and dispatches one or more younger micro instructions therein that depend on the load micro instruction for execution after a number of clock cycles following dispatch of the first load micro instruction, and if it is indicated on the hold bus that the load micro instruction is the specified load micro instruction, the second reservation station is configured to stall dispatch of the one or more younger micro instructions until the load micro instruction has retrieved the operand. The resources include an input/output (I/O) unit, configured to perform I/O operations via an I/O bus coupling an out-of-order processor to I/O resources.
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5.发明公开MECHANISM TO PRECLUDE LOAD REPLAYS DEPENDENT ON PAGE WALKS IN OUT-OF-ORDER PROCESSOR 审中-公开机械制造商VON LASTWIEDERHOLUNGABHÄNGIGVON PAGEWALKS BEI EINEM超低价供应商
公开(公告)号：EP3055769A1
公开(公告)日：2016-08-17
申请号：EP14891601.8
申请日：2014-12-14
发明人： COL, Gerard, M. , EDDY, Colin , HENRY, G., Glenn
IPC分类号： G06F9/38
CPC分类号： G06F9/3855 , G06F1/3228 , G06F1/3296 , G06F9/30043 , G06F9/30101 , G06F9/38 , G06F9/3824 , G06F9/3836 , G06F9/384 , G06F9/3861 , G06F12/0831 , G06F12/0875 , G06F12/1009
摘要： An apparatus including first and second reservation stations. The first reservation station dispatches a load micro instruction, and indicates on a hold bus if the load micro instruction is a specified load micro instruction directed to retrieve an operand from a prescribed resource other than on-core cache memory. The second reservation station is coupled to the hold bus, and dispatches one or more younger micro instructions therein that depend on the load micro instruction for execution after a number of clock cycles following dispatch of the first load micro instruction, and if it is indicated on the hold bus that the load micro instruction is the specified load micro instruction, the second reservation station is configured to stall dispatch of the one or more younger micro instructions until the load micro instruction has retrieved the operand. The resources include a system memory that is accessed via a memory bus, the system memory comprising one or more page tables, configured to store one or more mappings between virtual addresses and physical addresses.
摘要翻译： 一种包括第一和第二保留站的装置。 第一保留站调度负载微指令，并且如果负载微指令是指定的从指定的资源而不是内核高速缓冲存储器检索操作数的指定负载微指令，则指示保持总线。 第二保留站耦合到保持总线，并且在分配第一加载微指令之后的数个时钟周期之后，发送依赖于负载微指令的一个或多个更小的微指令，并且如果在 所述保持总线，所述加载微指令是指定的加载微指令，所述第二保留站被配置为停止所述一个或多个较小的微指令的分派，直到所述加载微指令已经检索到所述操作数。 资源包括通过存储器总线访问的系统存储器，所述系统存储器包括一个或多个页表，其被配置为存储虚拟地址和物理地址之间的一个或多个映射。
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6.发明公开MECHANISM TO PRECLUDE UNCACHEABLE-DEPENDENT LOAD REPLAYS IN OUT-OF-ORDER PROCESSOR 审中-公开机制，撤除不会持续可储存REPRODUCTIONS在处理器中的服务
公开(公告)号：EP3055768A1
公开(公告)日：2016-08-17
申请号：EP14891600.0
申请日：2014-12-14
发明人： COL, Gerard, M. , EDDY, Colin , HENRY, G., Glenn
CPC分类号： G06F9/3838 , G06F9/30043 , G06F9/3824 , G06F9/3834 , G06F9/3836 , G06F9/3855 , G06F9/3861
摘要： An apparatus including first and second reservation stations. The first reservation station dispatches a load micro instruction, and indicates on a hold bus if the load micro instruction is a specified load micro instruction directed to retrieve an operand from a prescribed resource other than on-core cache memory. The second reservation station is coupled to the hold bus, and dispatches one or more younger micro instructions therein that depend on the load micro instruction for execution after a number of clock cycles following dispatch of the first load micro instruction, and if it is indicated on the hold bus that the load micro instruction is the specified load micro instruction, the second reservation station is configured to stall dispatch of the one or more younger micro instructions until the load micro instruction has retrieved the operand. The resources include system memory, coupled an out-of-order processor via a memory bus.
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