公开(公告)号：EP0051960A1

公开(公告)日：1982-05-19

申请号：EP81305108.3

申请日：1981-10-28

申请人： XEROX CORPORATION

发明人： Lam, Kai Yiu ,  Mager, George Edward

IPC分类号： G06F3/04 ,  H04L11/16

CPC分类号： H04L12/413 ,  G06F13/376

摘要： A shared line transmitter is operative to accept as a message one or more bytes of data in parallel from an input-output channel for predetermined buffering and phase encoding for transmission to a shared line except upon receipt of signal indicating that another transmitter is attempting to gain access to the shared line. It includes an output buffer operative to receive the message from the input-output channel and hold it for a predetermined period; a memory operative to receive the message from the output buffer and hold it for a predetermined period for subsequent transmission in serial form; a phase encoder operative to receive the data in serial form for conversion to a predetermined phase-encoded form for outputting to the shared line. and means for aborting the conversion upon receipt of a message-collision signal for transmitting a signal onto the shared line to abort all concurrent message transmissions, and backoff logic operative to receive the abort signal from the phase encoder to generate a random number representing the period that must elapse before the next transmission.

摘要翻译： 共享线路发射机可操作以接收来自输入 - 输出信道的一个或多个数据字节作为消息，用于预定的缓冲和相位编码以传输到共享线路，除了接收到指示另一个发射机试图获得的信号 访问共享线路。 它包括输出缓冲器，用于从输入 - 输出通道接收消息并将其保持预定的时间段; 存储器，其用于从所述输出缓冲器接收所述消息并将其保持预定的时间段以用于后续的串行传输; 用于以串行形式接收数据以转换为用于输出到共享线路的预定相位编码形式的相位编码器，以及用于在接收到用于将信号发送到共享线路上的消息冲突信号时中止该转换的装置， 中止所有并发消息传输，并且退避逻辑可操作以从相位编码器接收中止信号，以生成表示在下次发送之前必须经过的周期的随机数。

公开(公告)号：EP0053439A2

公开(公告)日：1982-06-09

申请号：EP81305265.1

申请日：1981-11-05

申请人： XEROX CORPORATION

发明人： Lam, Kai Yiu ,  Mager, George Edward

IPC分类号： G06F3/04

CPC分类号： G06F13/4213

摘要： shared line receiver module, operative to accept phase-encoded bits serially from a shared line for predetermined buffering and subsequent transferral in parallel to an input-output channel, includes a decoder operative to receive phase transitions of a signal from the shared line for conversion Into a predetermined series of logic signals; a first memory operative to receive the predetermined series of logic signals for the holding thereof for a predetermined period; an address recognizer operative to receive a first byte of the predetermined series of logic signals from the first memory indicating the destination address when available for holding thereof for a predetermined period, and an identification address register operative to receive an address from the input-output channel for uniquely identifying the shared line receiver, and for comparing with identification address in said address recognized for the predetermined series of logic signals to the input-output channel when an address match is obtained.

摘要翻译： 共享线路接收机模块，用于从共享线路串行地接受用于预定缓冲的并行并行的输入 - 输出信道的相位编码位，包括解码器，用于接收来自共享线路的信号的相位转换用于转换 成为一系列预定的逻辑信号; 第一存储器，用于在预定时间段内接收预定的一系列逻辑信号以保持其; 地址识别器，用于从预定的一系列逻辑信号的第一个字节接收指示目的地地址的第一个字节，当第一个字节可用于保持一段预定时间时，地址识别器可以从输入输出通道接收地址 用于唯一地识别共享线路接收机，并且用于当获得地址匹配时与所识别的用于预定系列逻辑信号的所述地址中的识别地址与输入 - 输出信道进行比较。

公开(公告)号：EP0053439A3

公开(公告)日：1982-08-11

申请号：EP81305265

申请日：1981-11-05

申请人： XEROX CORPORATION

发明人： Lam, Kai Yiu ,  Mager, George Edward

IPC分类号： G06F03/04

CPC分类号： G06F13/4213

摘要： shared line receiver module, operative to accept phase-encoded bits serially from a shared line for predetermined buffering and subsequent transferral in parallel to an input-output channel, includes a decoder operative to receive phase transitions of a signal from the shared line for conversion Into a predetermined series of logic signals; a first memory operative to receive the predetermined series of logic signals for the holding thereof for a predetermined period; an address recognizer operative to receive a first byte of the predetermined series of logic signals from the first memory indicating the destination address when available for holding thereof for a predetermined period, and an identification address register operative to receive an address from the input-output channel for uniquely identifying the shared line receiver, and for comparing with identification address in said address recognized for the predetermined series of logic signals to the input-output channel when an address match is obtained.

摘要翻译： 共享线路接收机模块，用于从共享线路串行地接受用于预定缓冲的并行并行的输入 - 输出信道的相位编码位，包括解码器，用于接收来自共享线路的信号的相位转换用于转换 成为一系列预定的逻辑信号; 第一存储器，用于在预定时间段内接收预定的一系列逻辑信号以保持其; 地址识别器，用于从预定的一系列逻辑信号的第一个字节接收指示目的地地址的第一个字节，当第一个字节可用于保持一段预定时间时，地址识别器可以从输入输出通道接收地址 用于唯一地识别共享线路接收机，并且用于当获得地址匹配时与所识别的用于预定系列逻辑信号的所述地址中的识别地址与输入 - 输出信道进行比较。