专利检索 ap:("Xilinx, Inc.") AND inv:"WU, Zhaoyin D." 第 1 页

1.

发明公开
CONTINUOUS TIME LINEAR EQUALIZATION (CTLE) ADAPTATION ALGORITHM ENABLING BAUD-RATE CLOCK DATA RECOVERY (CDR) LOCKED TO CENTER OF EYE 审中-公开

公开(公告)号：EP4014453A1

公开(公告)日：2022-06-22

申请号：EP20804368.7

申请日：2020-10-06

申请人： Xilinx, Inc.

发明人： WU, Zhaoyin D. , UPADHYAYA, Parag

IPC分类号： H04L25/03 , H04L7/00

2.

发明公开
BUILT-IN EYE SCAN FOR ADC-BASED RECEIVER 审中-公开

公开(公告)号：EP3500867A1

公开(公告)日：2019-06-26

申请号：EP17777452.8

申请日：2017-09-13

申请人： Xilinx, Inc.

发明人： ZHANG, Hongtao , WU, Zhaoyin D. , BORRELLI, Christopher J. , ZHANG, Geoffrey

IPC分类号： G01R31/02 , H04L7/00

3.

发明公开
PROGRAMMABLE DIGITAL SIGMA DELTA MODULATOR 审中-公开

公开(公告)号：EP3804142A1

公开(公告)日：2021-04-14

申请号：EP19730638.4

申请日：2019-05-24

申请人： Xilinx, Inc.

发明人： MEGAWER, Karim M. , UPADHYAYA, Parag , TURKER MELEK, Didem Z. , WU, Zhaoyin D.

IPC分类号： H03M3/00 , H03M7/36 , H03L7/197

4.

发明公开
HIGH QUALITY FACTOR INDUCTIVE AND CAPACITIVE CIRCUIT STRUCTURE 审中-公开
标题翻译：高品质因数电感和电容的电路结构

公开(公告)号：EP3075008A1

公开(公告)日：2016-10-05

申请号：EP14745302.1

申请日：2014-07-09

申请人： Xilinx, Inc.

发明人： JING, Jing , WU, Shuxian , WU, Zhaoyin D.

IPC分类号： H01L27/01 , H01L23/522 , H01L49/02 , H05K1/16 , H03H7/01

CPC分类号： H03H7/0115 , H01L23/5223 , H01L23/5227 , H01L27/016 , H01L28/10 , H01L28/60 , H01L28/88 , H01L2924/0002 , H03H5/02 , H03H7/0138 , H05K1/16 , Y10T29/49117 , H01L2924/00

摘要： A circuit includes a first finger capacitor (100) having a first bus line (110) coupled to a first plurality of finger elements (120) and a second bus line (105) coupled to a second plurality of finger elements (115). The first bus line is parallel to the second bus line. The circuit further includes an inductor (500) having a first leg (125, 515) oriented perpendicular to the first bus line and the second bus line. The first leg of the inductor is coupled to a center (135) of the first bus line. Related methods are also disclosed.