公开(公告)号：EP2838114A3

公开(公告)日：2015-04-08

申请号：EP14180536.6

申请日：2014-08-11

申请人： Xintec Inc.

发明人： HUANG, Yu-Lung ,  LIN, Chao-Yen ,  SUEN, Wei-Luen ,  CHEN, Chien-Hui

IPC分类号： H01L23/31 ,  H01L23/00

CPC分类号： H01L23/3114 ,  H01L23/3171 ,  H01L23/525 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/24 ,  H01L24/48 ,  H01L29/0657 ,  H01L2224/02371 ,  H01L2224/02375 ,  H01L2224/02379 ,  H01L2224/03002 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05548 ,  H01L2224/05571 ,  H01L2224/06164 ,  H01L2224/16013 ,  H01L2224/16105 ,  H01L2224/24226 ,  H01L2224/48227 ,  H01L2224/811 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/10156 ,  H01L2924/13091 ,  H01L2924/15788 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/03

摘要： An embodiment of the invention provides a chip package including a semiconductor substrate (100) having a first surface (100a) and a second surface (100b) opposite thereto. A dielectric layer (130) is overlying the first surface of the semiconductor substrate and comprises an opening exposing a conducting pad (150). A side recess (200) is on at least a first side of the semiconductor substrate, wherein the side recess extends from the first surface (100a) towards the second surface (100b). An upper recess is on at least a first side of the dielectric layer outside the conducting pad. A conducting layer is electrically connected to the conducting pad (150) and extends to the upper recess and the side recess.

公开(公告)号：EP2838114A2

公开(公告)日：2015-02-18

申请号：EP14180536.6

申请日：2014-08-11

申请人： Xintec Inc.

发明人： HUANG, Yu-Lung ,  LIN, Chao-Yen ,  SUEN, Wei-Luen ,  CHEN, Chien-Hui

IPC分类号： H01L23/31

CPC分类号： H01L23/3114 ,  H01L23/3171 ,  H01L23/525 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/24 ,  H01L24/48 ,  H01L29/0657 ,  H01L2224/02371 ,  H01L2224/02375 ,  H01L2224/02379 ,  H01L2224/03002 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05548 ,  H01L2224/05571 ,  H01L2224/06164 ,  H01L2224/16013 ,  H01L2224/16105 ,  H01L2224/24226 ,  H01L2224/48227 ,  H01L2224/811 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/10156 ,  H01L2924/13091 ,  H01L2924/15788 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/03

摘要： An embodiment of the invention provides a chip package including a semiconductor substrate (100) having a first surface (100a) and a second surface (100b) opposite thereto. A dielectric layer (130) is overlying the first surface of the semiconductor substrate and comprises an opening exposing a conducting pad (150). A side recess (200) is on at least a first side of the semiconductor substrate, wherein the side recess extends from the first surface (100a) towards the second surface (100b). An upper recess is on at least a first side of the dielectric layer outside the conducting pad. A conducting layer is electrically connected to the conducting pad (150) and extends to the upper recess and the side recess.

摘要翻译： 本发明的实施例提供一种芯片封装，其包括具有第一表面（100a）和与其相对的第二表面（100b）的半导体衬底（100）。 电介质层（130）覆盖在半导体衬底的第一表面上，并且包括暴露导电焊盘（150）的开口。 侧凹部（200）位于半导体衬底的至少第一侧上，其中侧凹部从第一表面（100a）朝向第二表面（100b）延伸。 上部凹部位于导电垫外侧的介电层的至少第一侧。 导电层电连接到导电垫（150）并延伸到上凹部和侧凹槽。