公开(公告)号：EP2483785B1

公开(公告)日：2017-09-20

申请号：EP10822339.7

申请日：2010-09-20

Applicant: Micron Technology, Inc.

Inventor： JEDDELOH, Joseph, M.

IPC: G06F3/06 ,  G06F11/10

CPC classification number: G06F11/08 ,  G06F3/0616 ,  G06F3/064 ,  G06F3/0688 ,  G06F11/1028 ,  G06F11/108

公开(公告)号：EP2625804A1

公开(公告)日：2013-08-14

申请号：EP11831571.2

申请日：2011-10-06

Applicant: Cleversafe, Inc.

Inventor： GLADWIN, S., Christopher

IPC: H04K1/00

CPC classification number: H03M13/29 ,  G06F11/1028 ,  G06F11/1076 ,  G06F17/30194 ,  H03M13/05 ,  H03M13/1515 ,  H03M13/373 ,  H03M13/3761 ,  H04L45/24

Abstract: A method begins by a first device obtaining data for transmission to a second device and partitioning the data to produce a plurality of data portions. The method continues with the first device dispersed storage error encoding the plurality of data portions using a plurality of sets of error coding dispersal storage function parameters to produce a plurality of sets of encoded data slices and transmitting the plurality of sets of encoded data slices to the second device via a network. The method continues with a second device receiving at least a decode threshold number of encoded data slices and dispersed storage error decoding the at least a decode threshold number of encoded data slices to produce a decoded data portion for each set of the plurality of sets of encoded data slices. The method continues with the second device recapturing the data from a plurality of decoded data portions.

公开(公告)号：EP2187527A2

公开(公告)日：2010-05-19

申请号：EP09174357.5

申请日：2009-10-28

Applicant: FUJITSU LIMITED

Inventor： Ukai, Masaki

IPC: H03M13/15

CPC classification number: H03M13/1575 ,  G06F11/1028 ,  H03M13/1515

Abstract: An error judging circuit includes a first EOR circuit tree that generates a check bit of a correction code by polynomial remainder calculation with respect to a polynomial expression of an original code which is protected from an error with respect to data of m bit block unit by addition in a Galois extension field GF (2 m ) in S m EC-D m ED using Reed-Solomon code, a second EOR circuit tree for generating syndromes from S n =Y(α n ) with respect to code C(x) in which the check bit is added to the original code when a polynomial representation of a code which is to be detected an error and has a possibility that an error is mixed is Y(x), and an error detection circuit unit that detect if there is a one block error, a two block error, or no error based on whether or not an equation of syndromes S 1 2 =S 0 S 2 is satisfied.

Abstract translation: 错误判定电路包括第一EOR电路树，其通过多项式余数计算生成校正码的校验位，该原始码的原始码的多项式表达式相对于m位块单元的数据通过加法而被保护免于错误 在使用Reed-Solomon码的S m EC-D m ED中的Galois扩展字段GF（2m）中，使用第二EOR电路树，用于相对于代码C（x）从S n = Y（±n）生成校正子 当检测到错误的代码的多项式表示和混合错误的可能性为Y（x）时，校验位被添加到原始代码的错误检测电路单元，检测是否存在 基于是否满足综合征方程S 1 2 = S 0 S 2的方程组错误，两个块错误或没有错误。

公开(公告)号：EP0986783B1

公开(公告)日：2003-02-12

申请号：EP97951493.2

申请日：1997-11-24

Applicant: INTEL CORPORATION

Inventor： HAYEK, George, R. ,  VENKATARAMAN, Radhakrishnan ,  AJANOVIC, Jasmin

IPC: G06F11/08 ,  G11C29/00 ,  G06F11/10

CPC classification number: G06F11/106 ,  G06F11/1028 ,  G06F11/1052 ,  G11C29/52 ,  G11C2029/0409

Abstract: Error correction circuitry attempts to detect and correct on the fly erroneous words within random access memory (RAM) within a computer system. RAM errors are scrubbed or corrected back in the memory without delaying the memory access cycle. Rather, the address of the section or row of RAM that contains the correctable error is latched for later used by an interrupt-driven firmware memory-error scrub routine. This routine reads and rewrites each word within the indicated memory section-the erroneous word is read, corrected on-the-fly as it is read, and then rewritten back into memory correctly. If the size of the memory section exceeds a predetermined threshold, then the process of reading and re-writing that section is divided into smaller sub-processes that are distributed in time using a delayed interrupt mechanism. Duration of each memory scrubbing subprocess is kept short enough that the response time of the computer system is not impaired with the housekeeping task of scrubbing RAM memory errors. System management interrupts and firmware may be used to implement the memory-error scrub routine, which makes it independent of and transparent to the various operating systems that may be run on the computer system.

公开(公告)号：EP1141830A1

公开(公告)日：2001-10-10

申请号：EP99966405.5

申请日：1999-12-22

Applicant: INTEL CORPORATION

Inventor： HOLMAN, Thomas, J. ,  MACWILLIAMS, Peter, D.

IPC: G06F11/10

CPC classification number: G06F11/1028 ,  G06F11/1036

Abstract: A method and apparatus for detecting errors in data output from memory and a device failure in the memory. In the invention, a check code is generated based on data to be input to the memory. The check code is valid when equal to zero. The check code is inverted and input along with the data as a codeword to the memory in response to a write command. The codeword is output from the memory in response to a read command. The codeword output from memory indicates whether a device in memory has failed. The inverted check code included in the codeword output from memory is re-inverted. Information indicating whether the data included in the codeword output from memory includes an error is generated based on the data and the codeword including the check code.

公开(公告)号：EP0922251B1

公开(公告)日：2000-05-24

申请号：EP97936594.7

申请日：1997-08-06

Applicant: SIEMENS AKTIENGESELLSCHAFT

Inventor： KNEFEL, Hans-Werner

IPC: G06F11/10

CPC classification number: G06F11/1016 ,  G06F11/1028 ,  G11B20/1833

Abstract: The data contents of memory systems are mostly safeguarded via an EDC method. The memory system is structured such that the recognizability of multi-bit errors is improved considerably by the EDC method.

公开(公告)号：EP0986783A4

公开(公告)日：2000-05-10

申请号：EP97951493

申请日：1997-11-24

Applicant: INTEL CORP

Inventor： HAYEK GEORGE R ,  VENKATARAMAN RADHAKRISHNAN ,  AJANOVIC JASMIN

IPC: G06F11/10 ,  G06F11/08 ,  G11C29/00

CPC classification number: G06F11/106 ,  G06F11/1028 ,  G06F11/1052 ,  G11C29/52 ,  G11C2029/0409

Abstract: Error correction circuitry attempts to detect and correct on the fly erroneous words within random access memory (RAM) within a computer system. RAM errors are scrubbed or corrected back in the memory without delaying the memory access cycle. Rather, the address of the section or row of RAM that contains the correctable error is latched for later used by an interrupt-driven firmware memory-error scrub routine. This routine reads and rewrites each word within the indicated memory section-the erroneous word is read, corrected on-the-fly as it is read, and then rewritten back into memory correctly. If the size of the memory section exceeds a predetermined threshold, then the process of reading and re-writing that section is divided into smaller sub-processes that are distributed in time using a delayed interrupt mechanism. Duration of each memory scrubbing subprocess is kept short enough that the response time of the computer system is not impaired with the housekeeping task of scrubbing RAM memory errors. System management interrupts and firmware may be used to implement the memory-error scrub routine, which makes it independent of and transparent to the various operating systems that may be run on the computer system.

Abstract translation: 纠错电路试图检测并纠正计算机系统内随机存取存储器（RAM）内的错误字。 RAM内存错误会在内存中清理或更正，而不会延迟内存访问周期。 相反，包含可纠正错误的RAM或RAM行的地址被锁存，以供稍后由中断驱动的固件存储器错误擦除例程使用。 该例程读取并重写指定存储区中的每个单词 - 读取错误的单词，在读取时对其进行校正，然后正确地重新写入内存。 如果存储器部分的大小超过预定阈值，则读取和重写该部分的过程被分成更小的子过程，其使用延迟中断机制及时分配。 每个内存清理子进程的持续时间保持足够短，以免计算机系统的响应时间受到清理RAM内存错误的内务处理任务的影响。 系统管理中断和固件可以用来实现存储器错误清理例程，这使得它可以独立于计算机系统上运行的各种操作系统并且是透明的。

公开(公告)号：EP0989491A2

公开(公告)日：2000-03-29

申请号：EP99307483.0

申请日：1999-09-22

Applicant: SUN MICROSYSTEMS, INC.

Inventor： Cypher, Robert

IPC: G06F11/10

CPC classification number: G06F11/1028

Abstract: The bits of a data block are assigned to a plurality of logical groups such that at most one bit corresponding to a component is assigned to a logical group. This assignment ensures that a component failure may introduce at most one bit error to a logical group. A number of bits in a logical group is selected to reduce the number of check bits for a given number of data bits. Error correction may be performed within each logical group to correct single errors within the logical group. Because each logical group is assigned at most one bit corresponding to a component, component failures may be detected and corrected.

Abstract translation: 将数据块的位分配给多个逻辑组，使得至多一个对应于组件的位被分配给逻辑组。 该分配确保组件故障最多可能向逻辑组引入一个位错误。 选择逻辑组中的多个比特以减少给定数量的数据比特的校验比特数。 可以在每个逻辑组内执行纠错，以纠正逻辑组中的单个错误。 由于每个逻辑组最多分配一个与组件相对应的位，所以可以检测和校正组件故障。

公开(公告)号：EP0889407A2

公开(公告)日：1999-01-07

申请号：EP98305142.6

申请日：1998-06-29

Applicant: Sun Microsystems, Inc.

Inventor： Singhal, Ashok

IPC: G06F11/10

CPC classification number: G06F11/1028

Abstract: A system for N-bit part failure detection using n-bit error detecting codes where n is less than N is disclosed. In a computer system having storage devices N bits wide and an error detection and correction capability of less than N bits, bit assignments are made so that storage device failures will be detectable because of the manner the effect of a part failure is distributed among multiple codewords. Consequently 8 and 16 bit wide DRAMs may be used in a memory system using error detection and correction codes which are not capable of detecting 8 or 16 bit errors in a codeword, and still preserve the ability to detect the worst errors possibly caused by a part failure. Further, since error detection and correction codes with a predefined error detection and correction capability generally do not double in number of bits required when the data portion of a codeword doubles, the present invention allows use of the remaining bits when using larger data words, not only for special data, but also for another error detection and correction code for the special data, all still preserving the ability to detect any part failures, even when a part failure causes a number of total bit errors far exceeding the error detection capability of the error detection and correction codes.

Abstract translation: 公开了一种使用n比特小于N的n位错误检测码进行N位部分故障检测的系统。 在具有N位宽的存储设备和小于N位的错误检测和校正能力的计算机系统中，进行比特分配，使得存储设备故障将被检测到，因为部件故障的影响分布在多个码字之间 。 因此，可以使用不能检测码字中的8位或16位错误的错误检测和校正码的存储器系统中使用8位和16位宽的DRAM，并且仍然保留检测可能由一个部分引起的最差错误的能力 失败。 此外，由于具有预定义的错误检测和校正能力的错误检测和校正代码通常在码字的数据部分双倍时所需的位数不会增加一倍，所以本发明允许在使用较大的数据字时使用剩余的比特，而不是 仅用于特殊数据，而且对于特殊数据的另一个错误检测和校正代码，所有这些仍然保留检测任何部件故障的能力，即使部件故障导致远远超过了错误检测能力的数量的总位错误 错误检测和纠正码。

公开(公告)号：EP0491544B1

公开(公告)日：1998-03-11

申请号：EP91311675.2

申请日：1991-12-16

Applicant: MOTOROLA, INC.

Inventor： Gruender, Eugene H., Jr. ,  Kraft, Douglas R.

IPC: G06F11/10

CPC classification number: G06F11/1028