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公开(公告)号：EP1604282B1
公开(公告)日：2018-08-22
申请号：EP04714828.3
申请日：2004-02-26
IPC分类号： G06F11/16
CPC分类号： G06F1/3237 , G06F1/3203 , G06F1/3287 , G11C2207/2281 , Y02D10/126 , Y02D10/128 , Y02D10/171
摘要： A data processing apparatus and method are provided for recovering from errors in the data processing apparatus. The data processing apparatus comprises processing logic operable to perform a data processing operation, and a plurality of sampling circuits, each sampling circuit being located at a predetermined point in the processing logic and operable to sample a value of an associated digital signal generated by the processing logic at that predetermined point. Each of the sampling circuits includes a backup latch for storing a backup copy of the associated digital signal value, and at least one of the sampling circuits is operable to temporally sample the value of the associated digital signal at a first time and at at least one later time, and to store as a backup copy a selected one of the sampled values representing a correct value. The value of the associated digital signal sampled at the first time is initially output from that sampling circuit, and that sampling circuit is operable to determine an occurrence of an error in the value of the associated digital signal sampled at the first time, and to issue an error signal upon determination of that error. The data processing apparatus further comprises error recovery logic operable in response to the error signal to implement a recovery procedure during which selected sampling circuits output as their sampled associated digital signal value the value stored in their backup latch.
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2.发明公开
公开(公告)号：EP1604371A1
公开(公告)日：2005-12-14
申请号：EP04721230.3
申请日：2004-03-17
发明人： AUSTIN, Todd, Michael , BLAAUW, David, Theodore , MUDGE, Trevor, Nigel , FLAUTNER, Krisztian , SYLVESTER, Dennis, Michael
CPC分类号： G06F9/3869 , G06F9/3861 , G06F11/141 , G11C7/04 , G11C7/1006 , G11C7/1039 , G11C7/1045 , G11C7/22 , G11C29/028 , G11C29/50 , G11C29/50012 , G11C2207/2281
摘要： There is provided a memory for storing data comprising: a fast data reading mechanism operable to read a data value from said memory to generate a fast read result that is output from said memory for further processing; a slow data reading mechanism operable to read said data value from said memory to generate a slow read result available after said fast read result has been output for further processing, said slow data reading mechanism being less prone to error in reading said data value than said fast data reading mechanism; a comparator operable to compare said fast read result and said slow read result to detect if said fast read result differs from said slow read result; and error repair logic operable if said comparator detects that said fast read result differs from said slow read result to suppress said further processing using said fast read result, to output said slow read result in place of said fast read result and to restart said further processing based upon said slow read result.
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公开(公告)号：EP1604265A1
公开(公告)日：2005-12-14
申请号：EP04721233.7
申请日：2004-03-17
CPC分类号： G06F11/167 , G06F1/3203 , G06F1/3237 , G06F1/3287 , G06F9/3869 , G11C2207/2281 , Y02D10/128 , Y02D10/171 , Y02D50/20
摘要： There is provided an integrated circuit comprising: a plurality of processing stages, at least one of said processing stages having processing logic operable to perform a processing operation upon at least one processing stage input value to generate a processing logic output signal; and a low power mode controller operable to control said integrated circuit to switch between an operational mode in which said integrated circuit performs said processing operations and a standby mode in which said integrated circuit retains signals values but does not perform said processing operations; wherein said at least one of said processing stages has: a non-delayed latch operable to capture a non-delayed value of said processing logic output signal at a non-delayed capture time; and a delayed latch operable during said operational mode to capture a delayed value of said processing logic output signal at a delayed capture time, said delayed capture time being later than said non- delayed capture time, said non-delayed value being passed as a processing stage input value to a following processing stage before said delayed capture time and a difference between said non-delayed value and said delayed value being indicative of said, processing operation not being complete at said non-delayed capture time; said delayed latch is operable during said standby mode to retain said delayed value whilst said non-delayed latch is powered down and loses said non-delayed value; and said delayed latch is formed to have a lower power consumption.
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4.发明授权
公开(公告)号：EP1604371B1
公开(公告)日：2006-07-26
申请号：EP04721230.3
申请日：2004-03-17
发明人： AUSTIN, Todd, Michael , BLAAUW, David, Theodore , MUDGE, Trevor, Nigel , FLAUTNER, Krisztian , SYLVESTER, Dennis, Michael
CPC分类号： G06F9/3869 , G06F9/3861 , G06F11/141 , G11C7/04 , G11C7/1006 , G11C7/1039 , G11C7/1045 , G11C7/22 , G11C29/028 , G11C29/50 , G11C29/50012 , G11C2207/2281
摘要： There is provided a memory for storing data comprising: a fast data reading mechanism operable to read a data value from said memory to generate a fast read result that is output from said memory for further processing; a slow data reading mechanism operable to read said data value from said memory to generate a slow read result available after said fast read result has been output for further processing, said slow data reading mechanism being less prone to error in reading said data value than said fast data reading mechanism; a comparator operable to compare said fast read result and said slow read result to detect if said fast read result differs from said slow read result; and error repair logic operable if said comparator detects that said fast read result differs from said slow read result to suppress said further processing using said fast read result, to output said slow read result in place of said fast read result and to restart said further processing based upon said slow read result.
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5.发明公开SYSTEMATIC AND RANDOM ERROR DETECTION AND RECOVERY WITHIN PROCESSING STAGES OF AN INTEGRATED CIRCUIT 有权故障检测以及故障进行系统误差和随机误差在阶段处理的集成电路
公开(公告)号：EP1604281A1
公开(公告)日：2005-12-14
申请号：EP04721222.0
申请日：2004-03-17
IPC分类号： G06F11/00
CPC分类号： G06F11/1695 , G06F9/3861 , G06F9/3869 , G06F11/0721 , G06F11/0793 , G06F11/104 , G06F11/1608 , G06F11/167 , G06F11/183
摘要： An integrated circuit includes a plurality of processing stages each including processing logic (1014), a non-delayed signal-capture element (1016), a delayed signal-capture element (1018) and a comparator (1024). The non-delayed signal-capture element (1016) captures an output from the processing logic (1014) at a non-delayed capture time. At a later delayed capture time, the delayed signal-capture element (1018) also captures a value from the processing logic (1014). An error detection circuit (1026) and error correction circuit (1028) detect and correct random errors in the delayed value and supplies an error-checked delayed value to the comparator (1024). The comparator (1024) compares the error-checked delayed value and the non-delayed value and if they are not equal this indicates that the non-delayed value was captured too soon and should be replaced by the error-checked delayed value. The non-delayed value is passed to the subsequent processing stage immediately following its capture and accordingly error recovery mechanisms are used to suppress the erroneous processing which has occurred by the subsequent processing stages, such as gating the clock and allowing the correct signal values to propagate through the subsequent processing logic before restarting the clock. The operating parameters of the integrated circuit, such as the clock frequency, the operating voltage, the body biased voltage, temperature and the like are adjusted so as to maintain a finite non-zero error rate in a manner that increases overall performance.
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6.发明授权SYSTEMATIC AND RANDOM ERROR DETECTION AND RECOVERY WITHIN PROCESSING STAGES OF AN INTEGRATED CIRCUIT 有权故障检测以及故障进行系统误差和随机误差在阶段处理的集成电路
公开(公告)号：EP1604281B1
公开(公告)日：2006-08-09
申请号：EP04721222.0
申请日：2004-03-17
IPC分类号： G06F11/00
CPC分类号： G06F11/1695 , G06F9/3861 , G06F9/3869 , G06F11/0721 , G06F11/0793 , G06F11/104 , G06F11/1608 , G06F11/167 , G06F11/183
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公开(公告)号：EP1604265B1
公开(公告)日：2006-06-14
申请号：EP04721233.7
申请日：2004-03-17
CPC分类号： G06F11/167 , G06F1/3203 , G06F1/3237 , G06F1/3287 , G06F9/3869 , G11C2207/2281 , Y02D10/128 , Y02D10/171 , Y02D50/20
摘要： There is provided an integrated circuit comprising: a plurality of processing stages, at least one of said processing stages having processing logic operable to perform a processing operation upon at least one processing stage input value to generate a processing logic output signal; and a low power mode controller operable to control said integrated circuit to switch between an operational mode in which said integrated circuit performs said processing operations and a standby mode in which said integrated circuit retains signals values but does not perform said processing operations; wherein said at least one of said processing stages has: a non-delayed latch operable to capture a non-delayed value of said processing logic output signal at a non-delayed capture time; and a delayed latch operable during said operational mode to capture a delayed value of said processing logic output signal at a delayed capture time, said delayed capture time being later than said non- delayed capture time, said non-delayed value being passed as a processing stage input value to a following processing stage before said delayed capture time and a difference between said non-delayed value and said delayed value being indicative of said, processing operation not being complete at said non-delayed capture time; said delayed latch is operable during said standby mode to retain said delayed value whilst said non-delayed latch is powered down and loses said non-delayed value; and said delayed latch is formed to have a lower power consumption.
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8.发明公开ERROR DETECTION AND RECOVERY WITHIN PROCESSING STAGES OF AN INTEGRATED CIRCUIT 审中-公开故障检测以及故障在阶段处理的集成电路
公开(公告)号：EP1604282A1
公开(公告)日：2005-12-14
申请号：EP04714828.3
申请日：2004-02-26
IPC分类号： G06F11/16
CPC分类号： G06F1/3237 , G06F1/3203 , G06F1/3287 , G11C2207/2281 , Y02D10/126 , Y02D10/128 , Y02D10/171
摘要： A data processing apparatus and method are provided for recovering from errors in the data processing apparatus. The data processing apparatus comprises processing logic operable to perform a data processing operation, and a plurality of sampling circuits, each sampling circuit being located at a predetermined point in the processing logic and operable to sample a value of an associated digital signal generated by the processing logic at that predetermined point. Each of the sampling circuits includes a backup latch for storing a backup copy of the associated digital signal value, and at least one of the sampling circuits is operable to temporally sample the value of the associated digital signal at a first time and at at least one later time, and to store as a backup copy a selected one of the sampled values representing a correct value. The value of the associated digital signal sampled at the first time is initially output from that sampling circuit, and that sampling circuit is operable to determine an occurrence of an error in the value of the associated digital signal sampled at the first time, and to issue an error signal upon determination of that error. The data processing apparatus further comprises error recovery logic operable in response to the error signal to implement a recovery procedure during which selected sampling circuits output as their sampled associated digital signal value the value stored in their backup latch.
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