公开(公告)号：EP4390748A1

公开(公告)日：2024-06-26

申请号：EP23217567.9

申请日：2023-12-18

申请人： MediaTek Inc.

发明人： CHIN, Pang-Yen ,  LIN, Yu-Sian ,  ZENG, Ri-Cheng ,  CHENG, Chi-Shun ,  TSENG, Wei-Hsin ,  CHEN, Kuan-Ta ,  HU, Chia-Hsin

IPC分类号： G06F30/38 ,  G06F30/39 ,  G06F111/20 ,  G06F117/12 ,  G06F119/20

CPC分类号： G06F30/39 ,  G06F2111/2020200101 ,  G06F2117/1220200101 ,  G06F2119/2020200101 ,  G06F30/398 ,  G06F30/38

摘要： A method for designing an integrated circuit layout includes: generating an analog standard cell library and designing the integrated circuit layout by using at least the analog standard cell library, where the step of generating the analog standard cell library includes creating a target analog standard cell that is included in the analog standard cell library and does not violate layout rules of digital standard cells. Another method for designing an integrated circuit layout includes: generating a mixed-signal standard cell library and designing the integrated circuit layout by using at least the mixed-signal standard cell library, where the step of generating the mixed-signal standard cell library includes creating a target mixed-signal standard cell that is included in the mixed-signal standard cell library and does not violate layout rules of digital standard cells.

公开(公告)号：EP4356281A1

公开(公告)日：2024-04-24

申请号：EP22730990.3

申请日：2022-06-08

申请人： Università Degli Studi di Udine

发明人： SPECOGNA, Ruben ,  PITASSI, Silvano ,  PASSAROTTO, Mauro

IPC分类号： G06F30/23 ,  G06F30/36 ,  G06F115/12 ,  G06F117/12

CPC分类号： G06F30/23 ,  G06F30/36 ,  G06F2115/1220200101 ,  G06F2117/1220200101