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    METHOD AND APPARATUS FOR VERIFYING PLACEMENT OF CHIP COMPONENT ON PRINTED CIRCUIT BOARD
    1.
    发明公开
    METHOD AND APPARATUS FOR VERIFYING PLACEMENT OF CHIP COMPONENT ON PRINTED CIRCUIT BOARD 审中-实审

    公开(公告)号：EP4435662A1

    公开(公告)日：2024-09-25

    申请号：EP24160504.7

    申请日：2024-02-29

    Applicant: Samsung SDI Co., Ltd.

    Inventor： Lee, Eunsik

    IPC: G06F30/398 ,  G06F30/392 ,  G06F115/12 ,  G06F119/18

    CPC classification number: G06F30/392 ,  G06F2115/1220200101 ,  G06F2119/1820200101 ,  G06F30/398

    Abstract: Provided is a method of verifying component placement on a printed circuit board, PCB, the method including obtaining a preset separation distance criterion for an arrangement of chip components (10) designed to be mounted on the PCB, and based on the preset separation distance criterion for the arrangement of the chip components, checking whether a separation distance (5) between the chip components (10) satisfies the preset separation distance criterion, wherein the checking of whether the preset separation distance criterion is satisfied includes verifying, based on the preset separation distance criterion, whether the separation distance (5) between the chip components (10) that are placed to alternate with each other satisfies the preset separation distance criterion.

    RELIABILITY ASSESSMENT OF AN ELECTRONIC COMPONENT CARRIER OR A PACKAGE COMPRISING IT USING AI-SUPPORTED FINITE ELEMENT ANALYSIS
    3.
    发明公开
    RELIABILITY ASSESSMENT OF AN ELECTRONIC COMPONENT CARRIER OR A PACKAGE COMPRISING IT USING AI-SUPPORTED FINITE ELEMENT ANALYSIS 审中-实审

    公开(公告)号：EP4357961A1

    公开(公告)日：2024-04-24

    申请号：EP22201845.9

    申请日：2022-10-17

    Applicant: AT & S Austria Technologie & Systemtechnik Aktiengesellschaft

    Inventor： Krivec, Thomas ,  Zuendel, Julia ,  Tao, Qi

    IPC: G06F30/17 ,  G06F30/23 ,  G06F30/27 ,  G06F119/02 ,  G06F113/18 ,  G06F115/12

    CPC classification number: G06F2119/0220200101 ,  G06F30/17 ,  G06F30/23 ,  G06F30/27 ,  G06F2113/1820200101 ,  G06F2115/1220200101

    Abstract: A method for a reliability assessment of an electronic component carrier or a package comprising an electronic component carrier (1). The method comprises: providing a global simulation model of the component carrier or package (1), wherein a predetermined number of geometric properties of the component carrier or package (1) and of its constituent parts made of different materials and of physical properties of materials used in said constituent parts are defined as independent variables in a parameter space of the global simulation model; and wherein the global simulation model is configured to receive input data including a point in the parameter space and is configured to output data indicative of resulting geometric and/or physical properties within a global volume of the resulting component carrier or package (1). The method comprises running a simulation of the global simulation model and identifying, in its output data, boundary conditions for a plurality of local sub-portions (2) of the component carrier or package (1). The method further comprises providing at least one data-based local model for said local sub-portions (2), each data-based local model being trained to receive said boundary conditions as input data and provide a criticality value indicative of a reliability of the respective local sub-portion (2) as output data; running the at least one local data-based model for each of said local sub-portions (2) and identifying, in the respective output data, those local sub-portions (2) whose criticality value is above at least one predetermined threshold.

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