公开(公告)号：EP4435662A1

公开(公告)日：2024-09-25

申请号：EP24160504.7

申请日：2024-02-29

Applicant: Samsung SDI Co., Ltd.

Inventor： Lee, Eunsik

IPC: G06F30/398 ,  G06F30/392 ,  G06F115/12 ,  G06F119/18

CPC classification number: G06F30/392 ,  G06F2115/1220200101 ,  G06F2119/1820200101 ,  G06F30/398

Abstract: Provided is a method of verifying component placement on a printed circuit board, PCB, the method including obtaining a preset separation distance criterion for an arrangement of chip components (10) designed to be mounted on the PCB, and based on the preset separation distance criterion for the arrangement of the chip components, checking whether a separation distance (5) between the chip components (10) satisfies the preset separation distance criterion, wherein the checking of whether the preset separation distance criterion is satisfied includes verifying, based on the preset separation distance criterion, whether the separation distance (5) between the chip components (10) that are placed to alternate with each other satisfies the preset separation distance criterion.

公开(公告)号：EP3739497A2

公开(公告)日：2020-11-18

申请号：EP20184634.2

申请日：2018-12-13

Applicant: TactoTek Oy

Inventor： SINIVAARA, Hasse ,  HEIKKILÄ, Tuomas ,  KERÄNEN, Antti

IPC: G06F30/398 ,  B29C64/112 ,  B29C64/393 ,  B29K101/12 ,  B29L31/34 ,  B33Y10/00 ,  B33Y50/02 ,  G06F30/36 ,  G06F30/392 ,  G06F119/18 ,  G06F115/12

Abstract: An electronic arrangement for facilitating circuit layout design in connection with target designs, the arrangement including at least one communication interface for transferring data, at least one processor for processing instructions and other data, and a memory for storing the instructions and other data. The at least one processor being configured, in accordance with the stored instructions, to cause: obtaining and storing information in a data repository hosted by the memory, receiving design input characterizing target design to be produced from a substrate, determining a mapping between locations of the target design and the substrate, and establishing and providing digital output comprising human and/or machine readable instructions indicative of the mapping to a receiving entity, such as a manufacturing equipment, e.g. printing, electronics assembly and/or forming equipment.

公开(公告)号：EP4381416A1

公开(公告)日：2024-06-12

申请号：EP22754644.7

申请日：2022-07-21

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： VENKATRAMANI, Rajagopalan ,  GADDI, Renato Dimatula ,  SURELL, Dennis Glenn Lozanta ,  MARTINEZ, Liane

IPC: G06F30/394 ,  G06F30/398 ,  G06F113/18 ,  G06F115/12

CPC classification number: G06F30/394 ,  G06F30/398 ,  G06F2113/1820200101 ,  G06F2115/1220200101

公开(公告)号：EP4371026A1

公开(公告)日：2024-05-22

申请号：EP21769555.0

申请日：2021-08-17

Applicant: Siemens Industry Software Inc.

Inventor： SUITER II, Gerald P. ,  WEI, Wei ,  ROZWADOWSKI, Dariusz

IPC: G06F30/30 ,  G06F30/27 ,  G06F115/12 ,  G06F111/04

CPC classification number: G06F30/30 ,  G06F30/27 ,  G06F2111/0420200101 ,  G06F2115/1220200101

公开(公告)号：EP3841513B1

公开(公告)日：2024-04-17

申请号：EP19765948.5

申请日：2019-08-28

IPC: G06F30/39 ,  G06F111/20 ,  G06F115/12

CPC classification number: G06F30/39 ,  G06F2115/1220200101 ,  G06F2111/2020200101

公开(公告)号：EP4471656A1

公开(公告)日：2024-12-04

申请号：EP23176469.7

申请日：2023-05-31

Applicant: Airbus Operations GmbH

Inventor： Brückmann, Konstantin ,  Hahn, Dennis ,  Nitsche, Maximilian

IPC: G06F30/3947 ,  H05K1/00 ,  B64C1/06 ,  B64F5/00 ,  H05K1/02 ,  G06F113/16 ,  G06F113/24 ,  G06F113/26 ,  G06F113/28 ,  G06F115/12 ,  G06F119/18

Abstract: The present disclosure relates to a method for generating, according to an input specification, a layout of a laminated panel comprising a first layer providing a cover function, a second layer providing a support function and a third layer providing a routing function. The method comprises the steps of selecting a mounting surface to be equipped with at least one electrical function, wherein the first layer is a part of the mounting surface, superimposing, onto the selected mounting surface, a grid signifying at least one virtual interface and at least one virtual constraint for the at least one electrical function, receiving the input specification to select and place the at least one electrical function on the superimposed grid, transferring the at least one selected and placed electrical function into one or more modules to be placed on the grid, connecting the one or more modules with the routing function, and generating the layout comprising manufacturing specifications for the first, second and third layers. The present disclosure further relates to a computer-readable medium, a laminated panel, an apparatus and a system.

公开(公告)号：EP3043248B1

公开(公告)日：2024-04-03

申请号：EP14843126.5

申请日：2014-09-03

Inventor： JEONG, Joongki

IPC: G06F30/31 ,  H05K13/08 ,  G06F3/0484 ,  G01R31/309 ,  G01N21/956 ,  G06F30/398 ,  G06F115/12

公开(公告)号：EP4068137A1

公开(公告)日：2022-10-05

申请号：EP21812422.0

申请日：2021-05-31

Applicant: Koh Young Technology Inc.

Inventor： HAN, Guk ,  LEE, Jae Hwan ,  LEE, Duk Young ,  PARK, Chan Woo

IPC: G06F30/20 ,  G06F119/22 ,  G06F115/12

Abstract: An electronic apparatus according to various embodiments of the present disclosure may include: a communication circuit that is communicatively connected to a solder printing apparatus and a measurement apparatus; one or more memories; and one or more processors. One or more processors may be configured to: acquire a first control parameter set of the solder printing apparatus for printing solder on a first substrate; transmit information indicating the first control parameter set to the solder printing apparatus; acquire first solder measurement information indicating a state of the solder printed on the first substrate; determine a first yield for the first substrate based on the first solder measurement information; and generate a model for searching for an optimal control parameter set based on a first data pair including the first control parameter set and the first yield.

公开(公告)号：EP4485269A1

公开(公告)日：2025-01-01

申请号：EP24181945.7

申请日：2024-06-13

Applicant: MediaTek Inc.

Inventor： CHANG, Shu-Huan ,  CHEN, Yi-Hung ,  HSU, Chih-Jung ,  LIEN, Chen ,  FANG, Guan-Qi ,  TU, Deng-Yao ,  CHEN, Po-Yang

IPC: G06F30/31 ,  G06F30/398 ,  G06F111/02 ,  G06F115/12 ,  G06F119/18 ,  G06F113/18

Abstract: A method for performing automatic layout defect checking, ALDC, control regarding circuit design, associated apparatus and an associated computer-readable medium are provided. The method applicable to a processing circuit may include: providing a web-based entry in an ALDC control system running on a processing circuit, for any user among multiple users to upload at least a layout file of a package substrate design of at least one package substrate to the ALDC control system, in order to obtain at least the layout file from a client electronic device through the web-based entry (S11); utilizing at least one backend program module to check the layout file according to a plurality of predetermined layout defect checking rules to generate at least one checking result, and create a layout defect checking report of the package substrate design (S12); and sending the layout defect checking report corresponding to the layout file to the client electronic device (S13).

公开(公告)号：EP4381414A1

公开(公告)日：2024-06-12

申请号：EP22764921.7

申请日：2022-07-21

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： VENKATRAMANI, Rajagopalan ,  GADDI, Renato Dimatula ,  MARTINEZ, Liane ,  SANTOS, Warren Alexander ,  SURELL, Dennis Glenn Lozanta

IPC: G06F30/392 ,  G06F30/394 ,  G06F30/398 ,  G06F115/12 ,  G06F113/18

CPC classification number: G06F30/392 ,  G06F30/394 ,  G06F30/398 ,  G06F2115/1220200101 ,  G06F2113/1820200101