公开(公告)号：EP2284713A2

公开(公告)日：2011-02-16

申请号：EP10009998.5

申请日：1997-01-29

Applicant: Sony Electronics Inc.

Inventor： Smyers, Scott D. ,  Fairman, Bruce

IPC: G06F13/10

CPC classification number: G06F13/10 ,  G06F13/102 ,  G06F13/28 ,  H04L12/40058 ,  H04L12/40065 ,  H04L12/40123 ,  H04L49/90 ,  H04L49/901 ,  H04L49/9031 ,  H04L49/9047 ,  H04L69/32

Abstract: An application programming interface implements and manages isochronous and asynchronous data transfer operations between an application and a bus structure. During an asynchronous transfer the API includes the ability to transfer any amount of data between one or more local data buffers within the application and a range of addresses over the bus structure using one or more asynchronous transactions. An automatic transaction generator may be used to automatically generate the transactions necessary to complete the data transfer. The APT also includes the ability to transfer data between the application and another node on the bus structure isochronously over a dedicated channel. During an isochronous data transfer, a buffer management scheme is used to manage a linked list of data buffer descriptors. This linked descriptor list can form a circular list of buffers and include a forward pointer to the next buffer in the list and a backward pointer to the previous buffer in the list for each buffer. The linked descriptor list may all form a linear list to which the application can append additional buffers or remove existing buffers from the list. During isochronous transfers of data, the API provides implementation of a resynchronisation event in the stream of data allowing for resynchronisation by the application to a specific point within the data. Implementation is also provided for a callback routine for each buffer in the list which calls the application at a predetermined point during the transfer of data.

Abstract translation: 应用编程接口实施和管理应用和总线结构之间同步和异步数据传输操作。 在异步传输到API包括到应用程序内的一个或多个本地数据缓冲器和使用一个或多个异步事务的范围内通过总线结构地址之间传输数据的任何量的能力。 的自动交易发生器可以被用来自动生成要完成的数据传输的事务。 因此，APT包括对等时经由专用信道的应用程序和另一个节点上的总线结构之间传送数据的能力。 期间，在同步数据传输，一个缓冲区管理方案来管理数据缓冲区描述符的链表。 此链接描述符列表可形成缓冲剂的循环列表和包括前向指针指向列表中的下一个缓冲区和一个向后指向列表中的每一个缓冲区中的前缓冲器。 链接列表描述符可都形成该申请可以附加额外的缓冲器或从列表中删除现有的缓冲器的线性列表。 期间的数据的同步传输，该API提供执行数据由应用到所述数据内的特定点，允许再同步的流中的重新同步的事件。 因此，实现提供了一个回调例程在其中要求在预定点数据的传输过程中的应用程序列表中的每个缓冲区。

公开(公告)号：EP2045973A1

公开(公告)日：2009-04-08

申请号：EP07117776.0

申请日：2007-10-02

Applicant: Deutsche Thomson OHG

Inventor： Siemens, Eduard ,  Qiu, Xiaopeng

IPC: H04L12/56 ,  H04L1/18 ,  G06F5/12

CPC classification number: H04L1/1874 ,  G06F5/12 ,  G06F2205/062 ,  H04L1/1835 ,  H04L47/6245 ,  H04L49/90 ,  H04L49/901 ,  H04L49/9031 ,  H04L49/9047

Abstract: This invention relates to a design of an efficient buffer management model in order to increase the efficiency of data exchange between two process threads, - e.g. when implementing a network transport protocol stack.
This invention proposes to use an interconnected system of different kinds of memory buffers (100, 101, 102), implemented as asynchronous read/write ring buffers ARWRB. These buffers are organized in a way, in which data can be stored into the buffer or fetched from the buffer essentially avoiding synchronization means like mutexes or semaphores.
In contrast to the conventional buffer management model, three ring buffers, namely send ring buffer (100), send token ring buffer (101) and receive ring buffer (102), are used within the transport protocol stack.

Abstract translation: 本发明涉及一种高效的缓存器管理模型的设计，以增加两个处理线程之间的数据交换的效率 - E. G. 当实现一个网络传输协议栈。 本发明提出了作为异步读/写环形缓冲器ARWRB在不同种类的存储器缓冲器（100，101，102），来实现的互连的系统中使用。 这些缓冲器的方式，在该数据可被存储到从基本上避免同步缓存器中的缓冲或取出组织等手段或互斥信号量。 与此相反的常规缓冲器管理模式，三个环形缓冲器，即发送环形缓冲器（100），发送令牌环缓冲器（101）和接收环形缓冲区（102）的传送协议栈内被使用。

公开(公告)号：EP1832131A4

公开(公告)日：2008-05-07

申请号：EP05823956

申请日：2005-12-21

Applicant: RESEARCH IN MOTION LTD

Inventor： RYBAK MIKE ,  LEJEUNE JEFF ,  BYLSMA RODNEY ,  OLIVER ROB

IPC: H04Q7/32 ,  G06F12/00 ,  H04L12/54

CPC classification number: G06F12/023 ,  G06F2212/2022 ,  H04L49/90 ,  H04L49/9031 ,  H04L51/30 ,  H04L51/38

Abstract: A method of ensuring that data sent to a handheld wireless communications device is written to non-volatile memory is disclosed. In a device, where data is initially written to a first volatile memory and then written to a second volatile memory before being written from the second volatile memory to a non-volatile memory, software code is implemented that causes the writing of the data to non-volatile memory concurrently with the writing of the data to the second volatile memory. The software code may incorporate operating system commands (such as Windows OS).

公开(公告)号：EP1884085A1

公开(公告)日：2008-02-06

申请号：EP06758664.4

申请日：2006-04-25

Applicant: Level 5 Networks Inc.

Inventor： POPE, Steve ,  RIDDOCH, David ,  YU, Ching ,  ROBERTS, Derek

IPC: H04L12/56

CPC classification number: H04L63/10 ,  H04L47/50 ,  H04L49/90 ,  H04L49/901 ,  H04L49/9031 ,  H04L49/9063

Abstract: Roughly described, a network interface device receiving data packets from a computing device for transmission onto a network, the data packets having a certain characteristic, transmits the packet only if the sending queue has authority to send packets having that characteristic. The data packet characteristics can include transport protocol number, source and destination port numbers, source and destination IP addresses, for example. Authorizations can be programmed into the NIC by a kernel routine upon establishment of the transmit queue, based on the privilege level of the process for which the queue is being established. In this way, a user process can use an untrusted user-level protocol stack to initiate data transmission onto the network, while the NIC protects the remainder of the system or network from certain kinds of compromise.

公开(公告)号：EP1588533B1

公开(公告)日：2006-06-21

申请号：EP03789402.9

申请日：2003-12-23

Applicant: Rohde & Schwarz FTK GmbH

Inventor： SCHWIERTZ, Jacek ,  ZUREK-TERHARDT, Günther

IPC: H04L29/06 ,  H04L12/28 ,  H04L1/16

CPC classification number: H04H60/11 ,  H04H20/02 ,  H04H20/16 ,  H04H2201/70 ,  H04L29/06 ,  H04L47/10 ,  H04L47/14 ,  H04L47/26 ,  H04L49/90 ,  H04L49/9031 ,  H04L49/9057 ,  H04L69/16 ,  H04L69/161 ,  H04L69/163 ,  H04N21/44209 ,  H04N21/6131 ,  H04N21/6375 ,  H04N21/6377 ,  H04N21/64322 ,  H04N21/658

Abstract: A system and method for data transmission comprise at least one wired connection (4) between a server (1), operating on the TCP/IP protocol and an exchange (3) and at least one mono-directional radio connection between the exchange (3) and a client (2), operating with the TCP/IP protocol. On a transmission loss of a data packet in a mono-directional radio connection (5), a temporary additional connection (24), between the client (2) and the exchange (3), is established on the IP level, for a repeated transmission of the lost data packet. Transmission losses can be directly recognised by means of the above system and a repeat transmission initiated. The system generates no additional run-time for data buffering with an error-free transmission.

公开(公告)号：EP1604493A2

公开(公告)日：2005-12-14

申请号：EP03774453.9

申请日：2003-08-04

Applicant: INTEL CORPORATION

Inventor： WOLRICH, Gilbert ,  SWEENEY, John ,  GUILFORD, James ,  ROSENBLUTH, Mark ,  BERNSTEIN, Debra

IPC: H04L12/56 ,  G06F1/00

CPC classification number: H04L49/9047 ,  H04L49/90 ,  H04L49/901 ,  H04L49/9031

Abstract: A method of managing a free list and ring data structure, which may be used to store journaling information, by storing and modifying information describing a structure of the free list or ring data structure in a cache memory that may also be used to store information describing a structure of a queue of buffers.

公开(公告)号：EP1596514A2

公开(公告)日：2005-11-16

申请号：EP05106705.6

申请日：1999-04-20

Applicant: NIPPON TELEGRAPH AND TELEPHONE CORPORATION

Inventor： Otaka, Akihiro, c/o NTT Int. Prop. Center ,  Miki, Noriki, NTT Int. Prop. Center ,  Tamaki, Norio, c/o NTT Int. Prop. Center

IPC: H04J3/24 ,  H04L12/64

CPC classification number: H04J3/247 ,  H04J3/24 ,  H04L12/2801 ,  H04L47/13 ,  H04L47/50 ,  H04L47/522 ,  H04L47/6225 ,  H04L47/6235 ,  H04L47/624 ,  H04L49/9031

Abstract: A packet multiplexing apparatus is presented for multiplexing packets to be transmitted from a number of user facilities to a local service node in such a way to assure equal access to one output port for all the users. The apparatus is provided with input ports (1-0~1-(N-1)) for inputting a packet in a respective input port; buffer memories (3-0~3-(n-1)) provided for each input port for temporary storage of a packet; an output signal transmission circuit (4) for retrieving a packet from each buffer memory in a specific sequence; an output port (2) for transmitting packets output from the output signal transmission circuit; and a retrieval sequencing section (10 or 20 or 30) for controlling the specific sequence by changing a retrieving order of packets from buffer memories for each complete round of packet retrieval so that a frequency of the retrieving order for each input port is uniformly shared by the input ports.

公开(公告)号：EP1573985A1

公开(公告)日：2005-09-14

申请号：EP03812659.5

申请日：2003-12-10

Applicant: Koninklijke Philips Electronics N.V.

Inventor： LI, Qiong ,  VAN DER SCHAAR, Mihaela

IPC: H04L12/56

CPC classification number: H04L49/9052 ,  H04L49/90 ,  H04L49/901 ,  H04L49/9031

Abstract: A circular buffer, i.e., a chain of buffers forming a circle, is provided for managing packet loss detecting in Internet streaming. The detection latency is determined by the size of the buffer chain, which can be dynamically adapted to network conditions and application requirements. The present invention can achieve reasonable detection accuracy.

公开(公告)号：EP0991230A3

公开(公告)日：2005-06-15

申请号：EP99307622.3

申请日：1999-09-28

Applicant: STMicroelectronics, Inc.

Inventor： Kasper, Christian D

IPC: H04L12/44

CPC classification number: H04L49/9021 ,  H04L49/103 ,  H04L49/25 ,  H04L49/254 ,  H04L49/3009 ,  H04L49/90 ,  H04L49/9031 ,  H04L49/9047 ,  H04L49/9063 ,  H04L49/9068

Abstract: A method and system for routing network-based data arranged in frames is disclosed. A host processor analyzes transferred bursts of data and initiates an address and look up algorithm for dispatching the frame to a desired destination. A shared system memory existing between a network device, e.g., an HDLC controller, working in conjunction with the host processor, receives data, including any preselected address fields. The network device includes a plurality of ports. Each port includes a FIFO receive memory for receiving at least a first portion of a frame. The first portion of the frame includes data having the preselected address fields. A direct memory access unit transfers a burst of data from the FIFO receive memory to the shared system memory. A communications processor selects the amount of data to be transferred from the FIFO receive memory based on the desired address fields to be analyzed by the host processor.

公开(公告)号：EP1278353A3

公开(公告)日：2004-02-04

申请号：EP02254989.3

申请日：2002-07-16

Applicant: Avaya, Inc.

Inventor： Lanzafame, Christopher ,  Moran, Christopher B. ,  Szajdecki, Richard

IPC: H04L12/64 ,  H04J3/06

CPC classification number: H04L47/283 ,  H04J3/0632 ,  H04L29/06027 ,  H04L47/10 ,  H04L47/2416 ,  H04L47/30 ,  H04L47/32 ,  H04L49/90 ,  H04L49/9031 ,  H04L49/9052 ,  H04L65/80 ,  H04L2012/5649 ,  H04L2012/5667 ,  H04L2012/5671 ,  H04L2012/5681 ,  H04M7/006 ,  H04Q11/0478

Abstract: A variable-size jitter buffer is used to store information associated with a voice signal, facsimile signal or other received signal in a receiver of a packet-based communication system. The receiver determines an appropriate adjustment time for making an adjustment to the size of the buffer based at least in part on a result of a signal detection operation performed on the received signal. For example, in the case of a received voice signal, the determined adjustment time may be a time at which a state machine associated with a speech detector is in a "no speech" state. If the actual buffer size at the determined adjustment time is not within a designated range of a target computed at least in part based on one or more jitter measurements, the buffer size is adjusted at the determined adjustment time, e.g., by an amount representative of the difference between the actual buffer size and the target. The invention provides low-delay and low-complexity jitter buffering particularly well suited for use in an Internet Protocol (IP) receiver of a voice-over-IP system.