公开(公告)号：EP4435446A1

公开(公告)日：2024-09-25

申请号：EP24164532.4

申请日：2024-03-19

申请人： NXP B.V.

发明人： Makkar, Shikhar ,  Gupta, Chandan

IPC分类号： G01R31/3185 ,  G06F30/333

CPC分类号： G01R31/318563 ,  G01R31/318572 ,  G01R31/318558 ,  G01R31/318513 ,  G01R31/318547 ,  G01R31/318544 ,  G01R31/318533 ,  G06F30/333

摘要： An apparatus (110) and method (200) are provided for scan testing a system-on-chip (SoC) integrated circuit having first and second partitions coupled together across one or more inter-partition circuits, each of which includes a decompressor; a compactor; an INTEST scan chain and an EXTEST scan chain coupled in parallel between the decompressor circuit and compactor circuit; and digital test control access hardware connected between the decompressor circuit and each INTEST scan chain and configured to selectively disable each INTEST scan chain while each EXTEST scan chain continues to operate in response to a partition EXTEST mode signal having a first predetermined value.

公开(公告)号：EP4307158A3

公开(公告)日：2024-04-17

申请号：EP23212137.6

申请日：2017-06-19

申请人： Imagination Technologies Limited

发明人： Darbari, Ashish ,  Singleton, Iain

IPC分类号： G06F30/33 ,  G06F11/07 ,  G06F11/30 ,  G06F30/3323 ,  G06F30/333

CPC分类号： G06F11/076 ,  G06F11/3055 ,  G06F30/3323 ,  G06F30/333 ,  G06F30/33

摘要： A hardware monitor arranged to detect livelock in a hardware design for an integrated circuit. The hardware monitor includes monitor and detection logic configured to detect when a particular state has occurred in the hardware design; and assertion evaluation logic configured to periodically evaluate one or more assertions that assert a formal property related to reoccurrence of the particular state in the hardware design to detect whether the hardware design is in a livelock comprising the predetermined state. The hardware monitor may be used by a formal verification tool to exhaustively verify that the hardware design cannot enter a livelock comprising the predetermined state.

公开(公告)号：EP2951737B1

公开(公告)日：2024-08-28

申请号：EP14704226.1

申请日：2014-01-23

IPC分类号： G06F30/34 ,  G06F30/333

CPC分类号： G06F30/34 ,  G06F30/333

公开(公告)号：EP4361878A1

公开(公告)日：2024-05-01

申请号：EP23190064.8

申请日：2023-08-07

申请人： INTEL Corporation

发明人： HACK, Paul ,  ZICKEL, Scot ,  GIACOBBE, John ,  ZAND, Koby ,  RONEN, Ilan ,  TSUKERMAN, Leonid ,  JIMENEZ CHAVEZ, Carlos Alberto

IPC分类号： G06F30/333 ,  G01R31/28 ,  G06F30/394 ,  G06F30/398

CPC分类号： G06F30/333 ,  G06F30/398 ,  G01R31/28 ,  G06F30/394

摘要： Methods, apparatus, systems, and articles of manufacture are disclosed. An example apparatus includes interface circuitry to obtain circuitry logic, the circuitry logic including a plurality of circuit elements logically connected by a plurality of nodes; identifier circuitry to: identify a node within the plurality of nodes for elevation; and identify a layer of an integrated circuit; port adder circuitry to modify the circuitry logic by adding a signal port, the signal port corresponding to a physical terminal in the identified layer; connector circuitry to modify the circuitry logic by connecting the signal port to the identified node; and layout planner circuitry to determine a layout of the integrated circuit based on the modified circuitry logic.