公开(公告)号：EP4383119A1

公开(公告)日：2024-06-12

申请号：EP23199077.1

申请日：2023-09-22

申请人： INTEL Corporation

发明人： NAGAR, Krishna ,  KRUEGER, Nathan ,  PENG, Yi ,  GORDON, Brandon ,  VENKITASUBRAMANI, Anand

IPC分类号： G06F30/327

CPC分类号： G06F30/327 ,  G06F30/3323 ,  G06F2115/1020200101 ,  G06F2117/0820200101

摘要： Systems or methods of the present disclosure may provide efficient circuit implementation on processing circuitry. The processing circuitry may include a processor, a programmable hardware, or both. The systems and methods may include determining and removing unused and/or redundant portions of predefined software and hardware description instructions before implementing associated circuitry. The implemented circuitry may perform various functions including parsing, pipelining, deparsing, temporary storage and combining, math operations, or a combination thereof, among other things.

公开(公告)号：EP4404097A1

公开(公告)日：2024-07-24

申请号：EP24152431.3

申请日：2024-01-17

申请人： Arteris, Inc.

发明人： CHARIF, Amir ,  VAN RUYMBEKE, Xavier

IPC分类号： G06F30/327 ,  G06F30/3323 ,  G06F30/394 ,  G06F119/20 ,  G06F115/02

CPC分类号： G06F30/327 ,  G06F30/3323 ,  G06F30/394 ,  G06F2115/0220200101 ,  G06F2119/2020200101

摘要： System and methods are disclosed for generation and synthesis of networks, such as a network-on-chip (NoC), to generate a network description. The system generates a NoC from a set of physical constraints and performance constraints as well as a set of inputs to a sequencer. The system produces the NoC with all its elements. The resulting output includes placement of the elements on a floorplan of a chip that represents the network, such as the NoC.

公开(公告)号：EP4307158A3

公开(公告)日：2024-04-17

申请号：EP23212137.6

申请日：2017-06-19

申请人： Imagination Technologies Limited

发明人： Darbari, Ashish ,  Singleton, Iain

IPC分类号： G06F30/33 ,  G06F11/07 ,  G06F11/30 ,  G06F30/3323 ,  G06F30/333

CPC分类号： G06F11/076 ,  G06F11/3055 ,  G06F30/3323 ,  G06F30/333 ,  G06F30/33

摘要： A hardware monitor arranged to detect livelock in a hardware design for an integrated circuit. The hardware monitor includes monitor and detection logic configured to detect when a particular state has occurred in the hardware design; and assertion evaluation logic configured to periodically evaluate one or more assertions that assert a formal property related to reoccurrence of the particular state in the hardware design to detect whether the hardware design is in a livelock comprising the predetermined state. The hardware monitor may be used by a formal verification tool to exhaustively verify that the hardware design cannot enter a livelock comprising the predetermined state.