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1.发明公开Shift register latch circuit operable as a D-type edge trigger and counter comprising a plurality of such latch circuits 失效移在D触发器和计数器由多个这样的移位寄存器锁存器的的方式寄存器锁存电路。
公开(公告)号：EP0010599A1
公开(公告)日：1980-05-14
申请号：EP79103405.1
申请日：1979-09-12
发明人： Brown, David John , Walther, Ronald G. , Williams, Thomas Walter , Wrigglesworth, Michael Denis
摘要： A shift register latch circuit consists of a polarity hold latch (1) connected to a set/reset latch (2). The latches can be clocked with separate non-overlapping clock trains (+A, +B and +C) so that automatically generated test patterns can be applied to a scan input (s) to test the circuit. This conforms to the so-called Level Sensitive Scan Design (LSSD) rules. During system operation, the shift register latch circuit operates as a " D" type edge trigger by connecting the clock input (+ B) of the set/reset latch (2) to the clock (-C) supplied to the polarity hold latch (1). By connecting a number of shift register latches together a Johnson counter can be formed and by clocking all latches with a single oscillator, a series of non-overlapping clock trains can be produced. Implementations of the shift register latch in AND circuits or AND OR INVERT circuits are described.
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2.发明授权Shift register latch circuit operable as a D-type edge trigger and counter comprising a plurality of such latch circuits 失效移位寄存器电路作为D型边缘触发器和包含多个这种锁存电路的计数器可操作
公开(公告)号：EP0010599B1
公开(公告)日：1982-05-05
申请号：EP79103405.1
申请日：1979-09-12
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