公开(公告)号：EP0646286B1

公开(公告)日：2002-10-16

申请号：EP93915402.7

申请日：1993-06-17

申请人： HARRIS CORPORATION

发明人： BEASOM, James, Douglas 506 S. Wildwood Lane ,  McLACHLAN, Craig, James 3234 Sand Dunes Court

IPC分类号： H01L21/76 ,  H01L21/20

CPC分类号： H01L21/76 ,  H01L21/2007 ,  H01L21/46 ,  H01L21/76264 ,  H01L21/76275 ,  H01L21/76286 ,  Y10S148/012 ,  Y10S148/05 ,  Y10S438/938

摘要： Warpage in a bonded wafer is limited by maintenance of a stress compensation layer on the backside of the bonded wafer during device fabrication processing. One embodiment applies a sacrificial polysilicon layer over a stress compensation silicon dioxide layer for bonded silicon wafers. The fabrication processing consumes the polysilicon layer but not the stress compensation silicon dioxide.

摘要翻译： 通过在器件制造处理期间在接合晶片的背面维持应力补偿层来限制粘合晶片的翘曲。 一个实施例在用于粘结硅晶片的应力补偿二氧化硅层上施加牺牲多晶硅层。 制造工艺消耗多晶硅层，但不消耗应力补偿二氧化硅。

公开(公告)号：EP0646286A1

公开(公告)日：1995-04-05

申请号：EP93915402.0

申请日：1993-06-17

申请人： HARRIS CORPORATION

发明人： BEASOM, James, Douglas 506 S. Wildwood Lane ,  McLACHLAN, Craig, James 3234 Sand Dunes Court

IPC分类号： H01L21 ,  H01L27

CPC分类号： H01L21/76 ,  H01L21/2007 ,  H01L21/46 ,  H01L21/76264 ,  H01L21/76275 ,  H01L21/76286 ,  Y10S148/012 ,  Y10S148/05 ,  Y10S438/938

摘要： Warpage in a bonded wafer is limited by maintenance of a stress compensation layer on the backside of the bonded wafer during device fabrication processing. One embodiment applies a sacrificial polysilicon layer over a stress compensation silicon dioxide layer for bonded silicon wafers. The fabrication processing consumes the polysilicon layer but not the stress compensation silicon dioxide.

摘要翻译： 通过在器件制造处理期间在接合晶片的背面维持应力补偿层来限制粘合晶片的翘曲。 一个实施例在用于粘结硅晶片的应力补偿二氧化硅层上施加牺牲多晶硅层。 制造工艺消耗多晶硅层，但不消耗应力补偿二氧化硅。

公开(公告)号：EP2577719A1

公开(公告)日：2013-04-10

申请号：EP11722473.3

申请日：2011-06-01

申请人： Commissariat à l'Énergie Atomique et aux Énergies Alternatives

发明人： BISOTTO, Isabelle ,  FEUILLET, Guy

IPC分类号： H01L21/425 ,  H01L21/477

CPC分类号： H01L21/46 ,  H01L21/425 ,  H01L21/477 ,  H01L33/0083

摘要： The invention relates to a method for purifying an n-type substrate made of ZnO and/or ZnMgO for reducing or removing the residual extrinsic impurities of the substrate with a view to p type doping at least a portion of the substrate, wherein a reactive species having a strong chemical affinity with at least one of the residual extrinsic impurities and/or capable of creating crystalline defects is introduced into at least one area of the substrate, said reactive species consisting of P, thus creating at least one so-called "getter" zone in the substrate, said zone being capable of trapping said residual extrinsic impurities and/or in which zone the residual extrinsic impurities are trapped; the substrate then annealed to diffuse the residual extrinsic impurities toward the "getter" zone, and/or out of the "getter" zone, preferably toward at least one surface of the substrate. The invention further relates to a method for preparing a substrate made of p-doped ZnO and/or ZnMgO including at least one step of purifying an n-type substrate made of ZnO and/or ZnMgO by the above purification method, wherein one or more reactive specie(s) not limited to phosphorus alone is/are employed.

公开(公告)号：EP0842530A1

公开(公告)日：1998-05-20

申请号：EP95926351.0

申请日：1995-07-31

申请人： LITTON SYSTEMS CANADA LIMITED

发明人： FARRELL, James, F.

IPC分类号： H01L21 ,  H01L29

CPC分类号： H01L29/78696 ,  H01L21/383 ,  H01L21/46 ,  H01L21/465 ,  H01L29/66522 ,  H01L29/66969

摘要： During the formation of a self-aligned thin film transistor (50), the semiconductor material channel layer (58) on the gate insulating layer (56) has a passivation shield (PS) applied to it aligned with the gate electrode (54). The channel layer is then exposed to a reagent selected to yield a chemical reaction with the portions of the channel layer (58) not covered by the passivation shield (PS) causing removal of a component of the semiconductor material thereby to change the electical properties of those portions of the channel layer. In this manner, doped source and drain regions (60, 62) can be formed on opposite sides of the channel having edges that extend to the edges of the gate electrode avoiding any overlap therebetween and reducing the parasitic capacitance of the thin film transistor (50).