Abstract:
Dispositif (1) d'émission/réception d'ondes radar, en particulier de radars à modulation de fréquence: ■ un circuit (2) de génération d'ondes radar, comportant un oscillateur commandé en tension (6) couplé à un circulateur (8) lui-même relié à une antenne d'émission/réception (9) ; ■ un circuit de détection (3) comportant un premier mélangeur (15) alimenté par ledit circulateur (8) et ledit oscillateur commandé en tension (6), et dans lequel l'oscillateur commandé en tension (6) comporte une entrée d'injection (56) d'un signal élaboré par un circuit complémentaire (30), ledit circuit complémentaire (30) étant alimenté en entrée par le signal de sortie (10) de l'oscillateur commandé en tension (6), et comportant un second mélangeur (36) alimenté par deux signaux (33,38) élaborés à partir du signal de sortie (10) de l'oscillateur commandé en tension (6).
Abstract:
A digital frequency synthesizer circuit with spur compensation includes a demodulator circuit (118) for demodulating the output signal (116) of the synthesizer's accumulator (108). Demodulator (118) also inverts the signal, and provides an inverted demodulated output signal (142) which is then coupled to the synthesizer clock (124) after passing through a gain stage (122) in order to modulate the synthesizer clock (124) with a compensation signal (146). The compensated clock signal (140) is then sent to accumulator (108) in order to substantially cancel out any jitter in the accumulator's output signal (116). The modulation signal (MOD IN) which is digitally applied to accumulator (108) is applied in analog fashion to the gain stage (122) in order to prevent the desired modulation signal (MOD IN) from being canceled in the output signal (116).
Abstract:
The oscillating apparatus according to this invention comprises a pulse doped FET (1), and a series feedback capacitor (2) connected to the source of the pulse doped FET (1), the pulse doped FET is a FET formed on a pulse doped epitaxial layer including a channel layer (23) with a high carrier density, and a cap layer (24) with a low carrier density formed on the channel layer (23). The series feedback capacitor (2) is a variable capacitor whose capacitance value increases when a gate bias voltage of the pulse doped FET (1) is changed toward increase a drain current of the pulse doped FET (1). Consequently, it is possible to reduce phase noises by controlling only the gate bias with an oscillation frequency set at a required value. As a result, the merits of the MMIC can be sufficiently utilized without the necessity of externally adding a dielectric resonator.
Abstract:
A method for reducing spurious for a clock distribution system, the method including a) providing a system controller, b) providing clock distribution system, c) inputting characteristics of the clock distribution system in advance of operation thereof, d) calculating an expected level of the integer boundary spurious as a function of a fractional offset value, e) selecting an integer boundary solution based on the fractional offset value being within a preferred predetermined region, and f) programming the master clock subsystem and the one or more fractional synthesizers with the integer boundary solution, and g) repeating steps d) through f) as needed.
Abstract:
A voltage-controlled oscillator according to the present invention comprises: a transistor (5), where the drain electrode (D) is grounded, the gate electrode (G) is connected to a resonator (3) whose resonant frequency is adjustable according to a voltage applied to a voltage-dependent capacitance diode (D₁) electromagnetically coupled with the resonator (3), an output signal is output from the source electrode (S); a resistor connected (R₂) in gate bias circuit or source voltage supply circuit for detecting a low-frequency noise component generated in the transistor (5), where the detected low-frequency noise component is amplified and fed back to the voltage-dependent capacitance (D₁) so as to cancel a phase-noise component generated in the voltage-controlled oscillator. The above-descried voltage-controlled oscillator may be further provided with a reference crystal oscillator to which the voltage-controlled oscillator is phase-locked. Thus, a microwave voltage-controlled oscillator excellent in phase-noise characteristics of the oscillated frequency is accomplished though there is employed a GaAs FET which is not good in a low-frequency noise characteristic.
Abstract:
A phase noise detector for a signal having a carrier frequency, comprising a frequency discriminator producing a dispersed signal from the signal and a phase detector means (28) responsive to the carrier frequency in the signal and to a carrier suppressed signal to produce an output signal corresponding to the noise close to the carrier frequency in the signal, the carrier suppressed signal being produced by a carrier suppression means (30) responsive to two input signals, the input signals corresponding to the signal, one of the input signals being the dispersed signal.
Abstract:
An apparatus and method are provided for increasing the effective Q-value of an oscillator so that the required Q-value can be reached with the use of a low Q-value oscillator. In this apparatus and method, the FM noise is measured at the output of the oscillator by an FM detector and the output of the FM detector is fed back to the control input of the oscillator. By using this negative FM feedback, frequency variations in the oscillator output are suppressed by applying a correction signal at the control input of the oscillator. The amount of suppression depends on the loop gain of the FM feedback loop and the amount of suppression is proportional to the loop gain so that the effective Q-value of the oscillator is proportional to the loop gain. As a result of correcting the FM noise measured at the oscillator output by using a negative FM feedback loop, the effective Q-value of the oscillator corresponds to the original Q-value multiplied by the loop gain of the FM feedback loop so that the effective Q-value of the oscillator is increased.
Abstract:
A phase noise detector for a signal having a carrier frequency, comprising a frequency discriminator producing a dispersed signal from the signal and a phase detector means (28) responsive to the carrier frequency in the signal and to a carrier suppressed signal to produce an output signal corresponding to the noise close to the carrier frequency in the signal, the carrier suppressed signal being produced by a carrier suppression means (30) responsive to two input signals, the input signals corresponding to the signal, one of the input signals being the dispersed signal.