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68 条记录 (耗时 0.015 秒)

    BOOSTED RETURN TIME FOR FAST CHIRP PLL AND CALIBRATION METHOD
    2.
    发明公开
    BOOSTED RETURN TIME FOR FAST CHIRP PLL AND CALIBRATION METHOD 审中-公开

    公开(公告)号：EP3579011A1

    公开(公告)日：2019-12-11

    申请号：EP18305686.0

    申请日：2018-06-06

    申请人： NXP USA, Inc.

    发明人： VIGIER, Jean-Stéphane ,  SALLE, Didier ,  PAVAO-MOREIRA, Cristian ,  ORLANDO, Julien

    IPC分类号： G01S7/03 ,  G01S7/35 ,  G01S7/40 ,  G01S13/34 ,  G01S13/93 ,  H03L7/093 ,  H03B1/04 ,  H03C3/09 ,  H03L7/089 ,  G01S13/28

    摘要： A fast chirp Phase Locked Loop (70) with a boosted return time includes a Voltage Controlled Oscillator, VCO, (12) generating a Frequency Modulated Continuous Waveform, FMCW, (14). The VCO responds to a filtered output voltage (74) of a filter (72) connected to a charge pump (28). A digital controller (82) modifies the FMCW to generate a chirp phase (304) and a return phase (300). The chirp phase includes a first linear change of the FMCW from a start frequency (202) to a stop frequency (204). The return phase includes a second linear change of the FMCW from the stop frequency to the start frequency. A boost circuit (86) connects to the digital controller and the filter. The boost circuit supplies a boost current (98) during the return phase. The boost current is proportional to a return slope of the return phase and inversely proportional to a VCO gain of the VCO.

    MULTI-PATH DIGITAL PRE-DISTORTION
    4.
    发明公开
    MULTI-PATH DIGITAL PRE-DISTORTION 审中-公开
    多路数字预失真

    公开(公告)号：EP3072233A1

    公开(公告)日：2016-09-28

    申请号：EP14812076.9

    申请日：2014-11-20

    申请人： Xilinx, Inc.

    发明人： COPELAND, Gregory C.

    IPC分类号： H03F1/32 ,  H03F3/189 ,  H03F3/24 ,  H03B1/04 ,  H04L27/36

    CPC分类号： H04B1/0475 ,  H03F1/3241 ,  H03F1/3258 ,  H03F3/189 ,  H03F3/245 ,  H03F2200/111 ,  H03F2201/3209 ,  H03F2201/3212 ,  H03F2201/3224 ,  H03F2201/3233 ,  H04B1/04 ,  H04B1/0483 ,  H04B2001/0425 ,  H04L27/367

    摘要： An apparatus relates generally to multi-path digital predistortion. In this apparatus, a single-band digital predistorter engine has first and second sample paths. An input stage is coupled to receive input samples and configured to separate them into first samples and second samples. The input stage provides first and second magnitudes for the first and second samples, respectively. A first set of digital predistorters receives the first samples, the first magnitudes and the second magnitudes. A second set of digital predistorters receives the second samples, the second magnitudes and the first magnitudes. An output stage is coupled to receive predistorted outputs from the first set of digital predistorters and the second set of digital predistorters and is configured to provide a digital predistorted composite signal from the first set of digital predistorters and the second set of digital predistorters.

    摘要翻译： 一种设备通常涉及多频带数字预失真。 在该装置中，单波段数字预失真器引擎（400）具有第一和第二采样路径（481,482）。 输入级（491）被耦合以接收输入样本并被配置成将它们分成第一样本和第二样本。 输入级（491）分别提供第一和第二采样的第一和第二量值。 第一组数字预失真器（441,443）接收第一采样，第一量值和第二量值。 第二组数字预失真器（445,447）接收第二采样，第二量值和第一量值。 输出级（492）被耦合以接收来自第一组数字预失真器（441,443）和第二组数字预失真器（445,447）的预失真输出，并且被配置为从第一组提供数字预失真合成信号 数字预失真器（441,443）和第二组数字预失真器（445,447）。

    Oscillateur controlé en tension comprenant un circuit de compensation de l'éffet d'entrainement en fréquence
    5.
    发明授权
    Oscillateur controlé en tension comprenant un circuit de compensation de l'éffet d'entrainement en fréquence 有权
    用电路的电压控制振荡器，以补偿频率mitziehens的效果

    公开(公告)号：EP1552600B1

    公开(公告)日：2008-06-04

    申请号：EP03778388.3

    申请日：2003-10-14

    申请人： STMicroelectronics S.A.

    发明人： NAYLER, Peter

    IPC分类号： H03B1/04 ,  H03L7/099

    CPC分类号： H03L7/06 ,  H03B5/1215 ,  H03B5/1231 ,  H03B5/1243 ,  H03B2202/046 ,  H03B2202/088 ,  H03L7/099 ,  H03L7/18

    摘要： The invention concerns a method for stabilizing the operation of a voltage-controlled oscillator (VCO) monitored by a phase locked loop (PLL), the voltage-controlled oscillator delivering a RF signal and receiving via at least one disturbance path a frequency harmonics component equal or close to that of the RF signal, capable of disturbing its operation by injection pulling effect. The invention is characterized in that the method comprises a step which consists in injecting into the voltage-controlled oscillator a signal for compensating the injection pulling effect, whereof the phase and amplitude are adjusted to as to neutralize the effects of the disturbance harmonics component. The invention is applicable in particular to IQ phase modulation in radiotelephony.

    System and method for time dithering a digitally-controlled oscillator tuning input
    6.
    发明公开
    System and method for time dithering a digitally-controlled oscillator tuning input 审中-公开
    系统和方法，用于产生一个抖动信号到数字控制振荡器的调谐输入

    公开(公告)号：EP1255355A1

    公开(公告)日：2002-11-06

    申请号：EP01000127.9

    申请日：2001-04-26

    申请人： Texas Instruments Incorporated

    发明人： Staszewski, Robert B. ,  Maggio, Kenneth ,  Leipold, Dirk

    IPC分类号： H03L7/099 ,  H03L7/093 ,  H03B1/04

    CPC分类号： H03L7/093 ,  H03J2200/10 ,  H03L7/0991 ,  H03L2207/50

    摘要： A technique of time dithering a fully digitally-controlled oscillator (DCO) tuning input employs a shift register 1306 and a multiplexer 1308 responsive to a sigma-delta modulated delay control to minimize spurious tones generated by a DCO 200. The shift register 1306 is clocked via a divided-down high-frequency reference provided by the DCO 200 output signal. The multiplexer 1308 is clocked via a frequency reference that is reclocked and synchronized to the DCO 200 output signal. The multiplexer 1308 output is thus time dithered in response to a delay control to minimize perturbations caused by switching.

    摘要翻译： 的时间抖动全数字控制振荡器的技术（DCO）调谐输入使用的移位寄存器1306和多路复用器1308响应于Σ-Δ调制的延迟控制以最小化由DCO 200的移位寄存器1306产生的寄生音调被计时 通过由DCO 200输出的信号提供一个分频的高频参考。 多路转换器1308经由频率参考时钟所做的是时钟恢复和同步到DCO 200的输出信号。 多路转换器1308输出因此时间响应于延迟控制以最小化通过切换引起的扰动抖动。

    ELECTROSTATIC DISCHARGE CIRCUIT FOR HIGH SPEED, HIGH VOLTAGE CIRCUITRY
    8.
    发明公开
    ELECTROSTATIC DISCHARGE CIRCUIT FOR HIGH SPEED, HIGH VOLTAGE CIRCUITRY 失效
    电气放电电路基础上，高速高压电路

    公开(公告)号：EP0740859A4

    公开(公告)日：1998-04-22

    申请号：EP95906819

    申请日：1995-01-10

    申请人： ATMEL CORP

    发明人： PAYNE JAMES E ,  PATHAK SAROJ ,  ROSENDALE GLEN A

    IPC分类号： H01L27/088 ,  H01L21/8234 ,  H02H7/20 ,  H02H9/04 ,  H03K19/003 ,  H04B15/00 ,  H03B1/04 ,  H01C7/12 ,  H02H1/00 ,  H02H1/04 ,  H02H3/20 ,  H02H3/22 ,  H02H7/00 ,  H02H9/00 ,  H03K5/00 ,  H04B1/10

    CPC分类号： H03K19/00315 ,  H02H9/046

    摘要： A protection circuit includes a first controlled path for discharging negative ESD pulses introduced at a signal node (30). The first controlled path is from the signal node to (Vcc) via the source and drain electrodes of a first transistor (36). The gate of the transistor is at a soft ground by connection of the gate through a resistor (42) and an inverter (44) to a fixed voltage supply potential (Vcc). A second controlled path discharges positive ESD pulses via source and drain regions of serially connected second (50) and third (52) transistors to ground. The second transistor (50) has a gate tied at (Vcc) by means of a resistor (62) and an inverter (66) to ground. The third transistor (52) is at soft ground by means of a resistor (64) and inverter (68) to (Vcc). The third transistor is turned on by a positive voltage exceeding the threshold voltage of the third transistor, but the second transistor prevents damage to the third transistor by limiting the voltage applied to the third transistor. The protection circuit may include a third controlled path through a fourth transistor (54), if low voltage circuitry (32) is tied to the signal node (30). The fourth transistor (54) includes a gate that is tied high by connection of the gate to ground via a resistor (82) and inverter (84).

    Frequency converter capable of reducing noise components in local oscillation signals
    9.
    发明公开
    Frequency converter capable of reducing noise components in local oscillation signals 失效
    在lokalen Oszillatorsignalen的频率计算器zur Ra​​uschkomponentenreduzierung

    公开(公告)号：EP0726646A1

    公开(公告)日：1996-08-14

    申请号：EP96102089.8

    申请日：1996-02-13

    申请人： KABUSHIKI KAISHA TOSHIBA

    发明人： Takafumi, Yamaji, 220, Kuare Toshiba Motoyawata ,  Hiroshi, Tanimoto ,  Satoshi, Arai

    IPC分类号： H03B1/04 ,  H03D7/14

    CPC分类号： H03B1/04 ,  H03B2202/07 ,  H03D7/1433 ,  H03D7/1458 ,  H03D2200/0043

    摘要： A frequency converter (41A,41B,54A,54B,62,64) includes a high-frequency signal input circuit (10) for forming a high-frequency signal with bias voltage or current to output a bias-added high-frequency signal; a local oscillation signal input circuit (20) having a first element (28) for forming a local oscillation signal with bias voltage or current and a second element (21) for suppressing a noise component having a frequency near a even harmonic of a local oscillation frequency to output a bias-added and noise suppressed local oscillation signal; and a multiplication circuit (30) for multiplying the bias-added high-frequency signal and the bias-added and noise suppressed local oscillation signal.

    摘要翻译： 变频器（41A，41B，54A，54B，62,64）包括用于形成具有偏置电压或电流的高频信号的高频信号输入电路（10），以输出偏置相加的高频信号; 具有用于形成具有偏置电压或电流的本地振荡信号的第一元件（28）和用于抑制具有接近于本地振荡的偶次谐波频率的噪声分量的第二元件（21）的本地振荡信号输入电路（20） 频率输出偏置相加和噪声抑制的本地振荡信号; 以及用于将偏置相加的高频信号和偏置相加噪声抑制的本地振荡信号相乘的乘法电路（30）。