公开(公告)号：EP4388655A1

公开(公告)日：2024-06-26

申请号：EP22757742.6

申请日：2022-07-26

申请人： QUALCOMM Incorporated

发明人： BROWN JR., Gary Lee ,  PATEL, Chirag Dipak

IPC分类号： H03F1/02 ,  H03F1/22 ,  H03F1/32 ,  H03F3/193 ,  H03F3/45 ,  H03G1/00 ,  H03F1/08 ,  H03F1/56

CPC分类号： H03F1/3288 ,  H03F1/3294 ,  H03F3/193 ,  H03F2200/29420130101 ,  H03F2200/19220130101 ,  H03F1/0294 ,  H03F2200/21320130101 ,  H03F2200/54620130101 ,  H03F1/223 ,  H03F2200/54120130101 ,  H03F3/45089 ,  H03F2203/4539420130101 ,  H03F2203/4531820130101 ,  H03G1/0023 ,  H03F2203/4522820130101 ,  H03F1/56 ,  H03F1/086

公开(公告)号：EP3909127B1

公开(公告)日：2024-05-29

申请号：EP19761843.2

申请日：2019-08-29

IPC分类号： H03F1/02 ,  H03F3/213 ,  H03F3/45 ,  H03F1/22

CPC分类号： H03F2200/2120130101 ,  H03F2200/1820130101 ,  H03F2203/2113120130101 ,  H03F2203/4511220130101 ,  H03F2203/4515420130101 ,  H03F2203/4524420130101 ,  H03F2203/4529220130101 ,  H03F2203/4539820130101 ,  H03F2203/4545420130101 ,  H03F2203/4550820130101 ,  H03F2203/4554120130101 ,  H03F3/213 ,  H03F1/0266 ,  H03F2203/4562120130101 ,  H03F2203/4517220130101 ,  H03F2200/53420130101 ,  H03F2200/54120130101 ,  H03F2203/4522820130101 ,  H03F2203/4573120130101 ,  H03F3/45179 ,  H03F1/223

公开(公告)号：EP4398483A2

公开(公告)日：2024-07-10

申请号：EP24177413.2

申请日：2019-08-29

申请人： Telefonaktiebolaget LM Ericsson (publ)

发明人： Elgaard, Christian ,  SJÖLAND, Henrik

IPC分类号： H03F1/22

CPC分类号： H03F2200/2120130101 ,  H03F2200/1820130101 ,  H03F2203/2113120130101 ,  H03F2203/4511220130101 ,  H03F2203/4515420130101 ,  H03F2203/4524420130101 ,  H03F2203/4529220130101 ,  H03F2203/4539820130101 ,  H03F2203/4545420130101 ,  H03F2203/4550820130101 ,  H03F2203/4554120130101 ,  H03F3/213 ,  H03F1/0266 ,  H03F2203/4562120130101 ,  H03F2203/4517220130101 ,  H03F2200/53420130101 ,  H03F2200/54120130101 ,  H03F2203/4522820130101 ,  H03F2203/4573120130101 ,  H03F3/45179 ,  H03F1/223

摘要： A bias circuit (200) for a PA (100) is disclosed. It comprises a first transistor (M1) having its drain terminal and its gate terminal connected to a first circuit node (x) and its source terminal connected to a first supply terminal (GND), a first current source (I1) connected to the first circuit node (x), and a digitally controllable first resistor (R1) connected between the first circuit node (x) and a second circuit node (y). It further comprises a second transistor (M2) configured to receive a first component (RFinp) of a differential input signal to the PA at its gate terminal, having its drain terminal connected to the second circuit node (y) and its source terminal connected to a second supply terminal (VDD), and a third transistor (M3) configured to receive a second component (RFinn) of the differential input signal to the PA at its gate terminal, having its drain terminal connected to the second circuit node (y) and its source terminal connected to a second supply terminal (VDD). The gate terminals of the second transistor (M2) and the third transistor (M3) are configured to be biased by a digitally controllable first voltage (V1). The bias circuit is configured to generate a bias voltage (Vbias) for the PA (100) at the second circuit node (y).