公开(公告)号：EP4423908A1

公开(公告)日：2024-09-04

申请号：EP22812923.5

申请日：2022-10-25

Applicant: QUALCOMM INCORPORATED

Inventor： KOPPASSERY, Girish ,  HUSAIN, Amjath ,  GAIKWAD, Abhay Shankar ,  DASGUPTA, Samiran ,  VALLABHANENI, Madhukar

IPC: H03F1/22 ,  H03F1/30 ,  H03F3/193

CPC classification number: H03F1/223 ,  H03F3/193 ,  H03F1/301 ,  H03F2200/45120130101 ,  H03F2200/29420130101 ,  H03F2200/44720130101 ,  H03F2200/45320130101 ,  H03F2200/45620130101

公开(公告)号：EP4350987A3

公开(公告)日：2024-07-03

申请号：EP24158832.6

申请日：2020-06-04

Applicant: Analog Devices International Unlimited Company

Inventor： ESMAEL, Mohamed

IPC: H03F1/02 ,  H03F3/193 ,  H03F1/32 ,  H03F3/21 ,  H03F3/24 ,  H03F1/30

CPC classification number: H03F1/0266 ,  H03F1/0288 ,  H03F3/193 ,  H03F1/3205 ,  H03F3/245 ,  H03F2200/10520130101 ,  H03F2200/29420130101 ,  H03F2200/45120130101 ,  H03F1/301 ,  H03F2200/1520130101 ,  H03F2200/1820130101 ,  H03F2200/2120130101 ,  H03F2200/55520130101

Abstract: Bias networks for amplifiers are disclosed. An example bias network includes an adaptive bias circuit, configured to generate a bias signal for an amplifier, and further includes a coupling circuit, configured to couple the adaptive bias circuit to the amplifier. The coupling circuit is made adaptive in that its' impedance depends on a power level of an input signal to be amplified by the amplifier. By configuring the coupling circuit to have a variable impedance that depends on the power level of the input signal, the coupling circuit may adapt to the input power level and, thereby, may modify the bias signal to reduce/optimize at least some of the nonlinearity that may be introduced to the bias signal by the adaptive bias circuit.

公开(公告)号：EP4391373A1

公开(公告)日：2024-06-26

申请号：EP22874685.5

申请日：2022-09-19

Applicant: Huawei Technologies Co., Ltd.

Inventor： REN, Zhixiong ,  LV, Yuyan ,  GUI, Xiaoyan

IPC: H03F1/32 ,  H03F3/193 ,  H03F3/21 ,  H03F3/45 ,  H03F3/24

CPC classification number: Y02D30/70 ,  H03F3/193 ,  H03F3/21 ,  H03F1/32 ,  H03F3/24 ,  H03F3/45

Abstract: This application provides a power amplification circuit, a power amplifier, and a transmitter. The power amplification circuit includes a power amplification unit and a compensation unit. The power amplification unit includes a first MOS field effect transistor, the compensation unit includes a third MOS field effect transistor, a source electrode of the third MOS field effect transistor is connected to a drain electrode of the first MOS field effect transistor, and a conductivity type of the third MOS field effect transistor is opposite to a conductivity type of the first MOS field effect transistor. Therefore, a change trend of a gate-source capacitor of the third MOS field effect transistor with an input voltage is opposite to a change trend of a gate-drain capacitor of the first MOS field effect transistor with the input voltage, to enable the gate-drain capacitor of the first MOS field effect transistor basically not to change with the input voltage after compensation, thereby compensating AM-PM and improving linearity of the power amplification circuit. In addition, a design of the power amplification circuit is simple.

公开(公告)号：EP3476041B1

公开(公告)日：2024-06-12

申请号：EP16738894.1

申请日：2016-06-28

IPC: H03F1/02 ,  H03F1/32 ,  H03F1/30 ,  H03F3/21 ,  H03F3/193 ,  H03F3/24

CPC classification number: H03F1/301 ,  H03F1/3205 ,  H03F3/193 ,  H03F3/211 ,  H03F3/245 ,  H03F2200/1820130101 ,  H03F2200/36620130101 ,  H03F2200/44720130101 ,  H03F2203/2113120130101 ,  H03F1/0288

公开(公告)号：EP2509215B1

公开(公告)日：2018-12-12

申请号：EP12161948.0

申请日：2012-03-29

Applicant: EM Microelectronic-Marin SA

Inventor： Buescher, Kevin Scott ,  Prokes, Michal

IPC: H03F1/02 ,  H03F1/22 ,  H03F1/32 ,  H03F3/193 ,  H04L27/04 ,  H03F3/72 ,  H03F3/24

CPC classification number: H03F1/0277 ,  H03F1/223 ,  H03F1/3205 ,  H03F3/193 ,  H03F3/245 ,  H03F3/72 ,  H03F2203/7206 ,  H03F2203/7236 ,  H04L27/04

Abstract: A power amplifier circuit can be linked to an antenna arrangement of a communication system for transmission of ASK RF data signals. The power amplifier circuit includes an amplifier core with several cascode amplifier cells in parallel. Each cascode amplifier cell is composed of three NMOS transistors in triode mounting between an output terminal connected to the antenna arrangement, and an earth terminal. A first transistor of each cascode amplifier cell is controlled by a carrier frequency signal, whereas a second transistor of each cascode amplifier cell is controlled by a smoothing control loop in order to modulate data to be transmitted on carrier frequency by amplitude shift keying. The smoothing control loop is provided for generating an increasing gate voltage for the second transistors on the basis of an increasing current ramp from a first minimum current value to a second maximum current value during a "0" to "1" data transition. The smoothing control loop is provided for generating a decreasing gate voltage for the second transistors on the basis of a decreasing current ramp from the second maximum current value to the first minimum current value during a "1" to "0" data transition for shaping the envelope of ASK RF data signals to be transmitted.

公开(公告)号：EP2909931B1

公开(公告)日：2018-12-05

申请号：EP13846821.0

申请日：2013-10-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： BROBSTON, Michael

IPC: H03F3/60 ,  H03F3/193

CPC classification number: H04B15/00 ,  H03F1/0222 ,  H03F3/193 ,  H03F3/245 ,  H03F3/607 ,  H03F2200/102

Abstract: A system and method amplify a waveform in a wireless network. An envelope of a waveform is detected to form an envelope waveform. The envelope waveform is shaped to form a shaped waveform, the shaping based on one or more characteristics of a distributed amplifier. The shaped waveform is filtered to form a filtered waveform. The filtered waveform is amplified to form a first amplified waveform. The distributed amplifier amplifies at least a part the waveform based on the first amplified waveform to form a second amplified waveform.

公开(公告)号：EP3396856A1

公开(公告)日：2018-10-31

申请号：EP18168897.9

申请日：2018-04-24

Applicant: Gatesair Inc.

Inventor： Cabrera, George ,  Borodulin, Dmitri

IPC: H03F1/02 ,  H03F1/42 ,  H03F3/193 ,  H03F3/26

CPC classification number: H03F1/0288 ,  H03F1/42 ,  H03F1/565 ,  H03F3/193 ,  H03F3/21 ,  H03F3/265 ,  H03F2200/06 ,  H03F2200/09 ,  H03F2200/387 ,  H03F2200/42 ,  H03F2200/451 ,  H03F2200/534 ,  H03F2200/541

Abstract: An amplification system includes a differential output circuit that provides an amplified output to drive a load. A main amplifier is coupled to a terminal of the differential output circuit via a main path, corresponding to a transmission line. A peak amplifier is coupled to another terminal of the differential output circuit via a peak path, corresponding to a transmission line. In a single-ended mode while the peak amplifier is deactivated for amplification purposes, the peak path performs an impedance inversion to effectively ground the other terminal of the differential output circuit. In a differential mode, each of the peak amplifier and the main amplifier operates to conduct current to respective terminals of the differential output circuit and each of the main path and the peak path provides a predetermined output impedance to the differential output circuit.

公开(公告)号：EP3394890A1

公开(公告)日：2018-10-31

申请号：EP16820474.1

申请日：2016-12-12

Applicant: Raytheon Company

Inventor： FLETCHER, David R. ,  HESTON, David D.

IPC: H01L23/66 ,  H03F1/18 ,  H03F3/195 ,  H03F3/60

CPC classification number: H03F1/0205 ,  H01L23/66 ,  H01L24/48 ,  H01L24/49 ,  H01L2223/6611 ,  H01L2223/665 ,  H01L2224/48227 ,  H01L2224/49111 ,  H01L2924/00014 ,  H01L2924/1423 ,  H01L2924/19105 ,  H01L2924/19107 ,  H03F1/0261 ,  H03F1/18 ,  H03F1/565 ,  H03F3/193 ,  H03F3/195 ,  H03F3/607 ,  H03F2200/108 ,  H03F2200/451 ,  H03F2200/555 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: Off-chip distributed drain biasing increases output power and efficiency for high power distributed amplifier MMICs. An off-chip bias circuit has a common input for receiving DC bias current and a plurality of parallel-connected bias chokes among which the DC bias current is divided. The chokes are connected to a like plurality of drain terminals at different FET amplifier stages to supply DC bias current at different locations along the output transmission line. Off-chip distributed drain biasing increases the level of DC bias current that can be made available to the amplifier and add inductances to selected FET amplifier stages, typically the earlier stages, to modify the load impedance seen at the drain terminal to better match the amplifier stages to improve power and efficiency.

公开(公告)号：EP3391536A1

公开(公告)日：2018-10-24

申请号：EP15831221.5

申请日：2015-12-17

Applicant: u-blox AG

Inventor： HAINE, John

IPC: H03F1/02 ,  H03F3/189 ,  H03F3/60

CPC classification number: H03F1/0288 ,  H03F3/16 ,  H03F3/189 ,  H03F3/193 ,  H03F3/211 ,  H03F3/602 ,  H03F3/604 ,  H03F2200/102 ,  H03F2203/21142

Abstract: An amplifier apparatus (332) comprises a main linear amplifier sub-circuit (402) having a main driving signal input terminal (331) and a main amplifier output terminal (406). The apparatus also comprises an auxiliary linear amplifier sub-circuit (404) having an auxiliary driving signal input terminal (357) and an auxiliary amplifier output terminal (408). A combining network (410) is operably coupled between the main amplifier output terminal (406) and the auxiliary amplifier output terminal (408), the combining network (410) having a main-side terminal (424) and an auxiliary-side terminal (434). The main linear amplifier sub-circuit (402) is arranged to generate, when in use, a main amplified signal in response to a main driving signal applied at the main driving signal input terminal (331). The auxiliary linear amplifier sub-circuit (404) is arranged to generate, when in use, an impedance modifying signal at the auxiliary-side terminal (357) in response to an auxiliary driving signal and at substantially the same time as the main linear amplifier sub-circuit (402) generates the main amplified signal, the auxiliary linear amplifier sub-circuit (404) also being arranged to amplify substantially more than half of each wave cycle of the auxiliary driving signal.

公开(公告)号：EP3389181A1

公开(公告)日：2018-10-17

申请号：EP17165827.1

申请日：2017-04-10

Applicant: HENSOLDT Sensors GmbH

Inventor： Wedemeyer, Markus ,  Sledzik, Hardy Hans

IPC: H03F1/02 ,  H03F1/32 ,  H03F1/34 ,  H03F3/193

CPC classification number: H03F1/0272 ,  H03F1/3217 ,  H03F1/34 ,  H03F3/193 ,  H03F2200/18 ,  H03F2200/27 ,  H03F2200/462 ,  H03F2200/481 ,  H03F2200/483 ,  H03F2200/78 ,  H03F2201/3209 ,  H03F2203/21161

Abstract: Eine Vorrichtung zur Regelung eines Ruhestromes (Io) durch einen Transistor (50) mit einem Steueranschluss (52) umfasst: eine Strommesseinrichtung (110) zum Erfassen einer Messgröße, die von dem Ruhestrom durch den Transistor (50) abhängt; eine Vergleichsschaltung (120) zum Vergleichen der erfassten Messgröße mit einem Sollwert; und eine Einstellschaltung (130), die ausgebildet ist, um in einem Ruhezustand des Transistors (50) in Abhängigkeit von dem Vergleich einen Spannungswert oder einen Stromwert an dem Steueranschluss (52) anzulegen, so dass der Ruhestrom (Io) durch den Transistor (50) in dem Ruhezustand einen gewünschten Wert aufweist.