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公开(公告)号：EP4358401A2
公开(公告)日：2024-04-24
申请号：EP24161505.3
申请日：2018-01-25
申请人： Analog Devices, Inc.
发明人： DAY, Christopher
IPC分类号： H03F1/32
CPC分类号： H03F1/0266 , H03F2203/4539220130101 , H03F2203/4545420130101 , H03F1/3211 , H03F3/19 , H03F2200/10220130101 , H03F2203/4511220130101 , H03F2203/4524420130101 , H03F2200/12920130101 , H03F2200/14420130101 , H03F2200/2120130101 , H03F2200/28520130101 , H03F2200/9920130101 , H03F3/45089 , H03F1/0222 , H03F1/22 , H03F3/21
摘要： A power amplifier circuit for broadband data communication over a path in a communication network can reduce or avoid gain compression, provide low distortion amplification performance, and can accommodate a wider input signal amplitude range. A dynamic variable bias current circuit can be coupled to a common emitter bias node of a differential pair of transistors to provide a dynamic variable bias current thereto as a function of an input signal amplitude of an input signal. Bias current is increased when input signal amplitude exceeds a threshold voltage established by an offset or level-shifting circuit. The frequency response of the bias current circuit can track the frequency content of the input signal. A delay in the signal path to the differential pair can phase-align the bias current to the amplification by the differential pair. A dynamic variable supply voltage can be based on an envelope of the input signal.
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公开(公告)号：EP3574582B1
公开(公告)日：2024-09-18
申请号：EP18744503.6
申请日：2018-01-25
CPC分类号： H03F1/0266 , H03F2203/4539220130101 , H03F2203/4545420130101 , H03F1/3211 , H03F3/19 , H03F2200/10220130101 , H03F2203/4511220130101 , H03F2203/4524420130101 , H03F2200/12920130101 , H03F2200/14420130101 , H03F2200/2120130101 , H03F2200/28520130101 , H03F2200/9920130101 , H03F3/45089 , H03F1/0222 , H03F1/22 , H03F3/21
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公开(公告)号：EP3909127B1
公开(公告)日：2024-05-29
申请号：EP19761843.2
申请日：2019-08-29
CPC分类号： H03F2200/2120130101 , H03F2200/1820130101 , H03F2203/2113120130101 , H03F2203/4511220130101 , H03F2203/4515420130101 , H03F2203/4524420130101 , H03F2203/4529220130101 , H03F2203/4539820130101 , H03F2203/4545420130101 , H03F2203/4550820130101 , H03F2203/4554120130101 , H03F3/213 , H03F1/0266 , H03F2203/4562120130101 , H03F2203/4517220130101 , H03F2200/53420130101 , H03F2200/54120130101 , H03F2203/4522820130101 , H03F2203/4573120130101 , H03F3/45179 , H03F1/223
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公开(公告)号：EP4398483A2
公开(公告)日：2024-07-10
申请号：EP24177413.2
申请日：2019-08-29
IPC分类号： H03F1/22
CPC分类号： H03F2200/2120130101 , H03F2200/1820130101 , H03F2203/2113120130101 , H03F2203/4511220130101 , H03F2203/4515420130101 , H03F2203/4524420130101 , H03F2203/4529220130101 , H03F2203/4539820130101 , H03F2203/4545420130101 , H03F2203/4550820130101 , H03F2203/4554120130101 , H03F3/213 , H03F1/0266 , H03F2203/4562120130101 , H03F2203/4517220130101 , H03F2200/53420130101 , H03F2200/54120130101 , H03F2203/4522820130101 , H03F2203/4573120130101 , H03F3/45179 , H03F1/223
摘要： A bias circuit (200) for a PA (100) is disclosed. It comprises a first transistor (M1) having its drain terminal and its gate terminal connected to a first circuit node (x) and its source terminal connected to a first supply terminal (GND), a first current source (I1) connected to the first circuit node (x), and a digitally controllable first resistor (R1) connected between the first circuit node (x) and a second circuit node (y). It further comprises a second transistor (M2) configured to receive a first component (RFinp) of a differential input signal to the PA at its gate terminal, having its drain terminal connected to the second circuit node (y) and its source terminal connected to a second supply terminal (VDD), and a third transistor (M3) configured to receive a second component (RFinn) of the differential input signal to the PA at its gate terminal, having its drain terminal connected to the second circuit node (y) and its source terminal connected to a second supply terminal (VDD). The gate terminals of the second transistor (M2) and the third transistor (M3) are configured to be biased by a digitally controllable first voltage (V1). The bias circuit is configured to generate a bias voltage (Vbias) for the PA (100) at the second circuit node (y).
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公开(公告)号：EP4358401A3
公开(公告)日：2024-07-10
申请号：EP24161505.3
申请日：2018-01-25
申请人： Analog Devices, Inc.
发明人： DAY, Christopher
CPC分类号： H03F1/0266 , H03F2203/4539220130101 , H03F2203/4545420130101 , H03F1/3211 , H03F3/19 , H03F2200/10220130101 , H03F2203/4511220130101 , H03F2203/4524420130101 , H03F2200/12920130101 , H03F2200/14420130101 , H03F2200/2120130101 , H03F2200/28520130101 , H03F2200/9920130101 , H03F3/45089 , H03F1/0222 , H03F1/22 , H03F3/21
摘要： A power amplifier circuit for broadband data communication over a path in a communication network can reduce or avoid gain compression, provide low distortion amplification performance, and can accommodate a wider input signal amplitude range. A dynamic variable bias current circuit can be coupled to a common emitter bias node of a differential pair of transistors to provide a dynamic variable bias current thereto as a function of an input signal amplitude of an input signal. Bias current is increased when input signal amplitude exceeds a threshold voltage established by an offset or level-shifting circuit. The frequency response of the bias current circuit can track the frequency content of the input signal. A delay in the signal path to the differential pair can phase-align the bias current to the amplification by the differential pair. A dynamic variable supply voltage can be based on an envelope of the input signal.
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