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    VARIABLE LENGTH ARBITRATION
    2.
    发明公开
    VARIABLE LENGTH ARBITRATION 有权
    可变长度评估

    公开(公告)号：EP2700014A1

    公开(公告)日：2014-02-26

    申请号：EP12773767.4

    申请日：2012-04-18

    申请人： Marvell World Trade Ltd.

    发明人： ZHU, Jun ,  CAO, Joseph Jun ,  LU, Sheng

    IPC分类号： G06F13/14

    CPC分类号： G06F13/362 ,  G06F12/00 ,  G06F13/14 ,  H03K17/62

    摘要： In one embodiment, a method determines a plurality of categories for requests for a shared resource being shared by a plurality of entities. A request for the resource is received from an entity in the plurality of entities. The method determines a category in the plurality of categories for the received request. If the received request is determined to be in a first category, the method dispatches the received request to a first arbitration scheme configured to determine an arbitration decision in a first time cycle. If the received request is determined to be in a second category, the method dispatches the received request to a second arbitration scheme configured to determine an arbitration decision in a second time cycle of a different length from the first time cycle.

    Befehlsgerät
    3.
    发明公开
    Befehlsgerät 失效
    命令单元

    公开(公告)号：EP0341689A3

    公开(公告)日：1991-05-22

    申请号：EP89108402.2

    申请日：1989-05-10

    申请人： Klöckner-Moeller GmbH

    发明人： Hoss, Michael, Dipl.-Ing.

    IPC分类号： H03K17/00 ,  G05B19/02 ,  G05B19/10

    CPC分类号： H03K17/62 ,  H03K17/296

    摘要： Ein Befehlsgerät mit elektronischen Schaltelementen weist eine Programmiereinrichtung 1 auf, mit der die Funktions­vorwahl für die elektronischen Schaltelemente K1K3 vor­genommen wird. Die Programmiereinrichtung 1 ist in dem Gehäuse integriert und beeinflußt eine für die Funktions­auswahl bestimmte Schaltungsanordnung Fig. 2, der als Funktionsangebot die Funktionen EIN/AUS, Takt, Impuls, Verzögert von den Funktionsblöcken 4, 5, 6, 7 zur Verfüg­ung gestellt werden. Das Befehlsgerät weist vor allem den Vorteil auf, daß eine Typenvielfalt vermieden wird und die Funktionsvorgabe direkt vom Anwender vorgenommen wird und jederzeit veränderbar ist. Die gesamte Schaltungsan­ordnung Fig. 1 ist als integrierter Schaltkreis ausge­führt und in dem Schaltgehäuse 21 untergebracht.

    摘要翻译： 具有电子开关元件的指令装置具有编程装置1，利用该编程装置1对电子开关元件K1K3进行功能预选。 编程装置1集成在壳体中并且影响图2的选择电路的特定功能，其作为功能提供功能块ON，OFF，时钟，脉冲，由功能块4,5,6,7延迟。 指令装置具有避免多种类型的特殊优点，并且功能说明由用户直接进行并且可以在任何时候改变。 整个电路布置图1被设计为集成电路并且被容纳在开关壳体21中。

    Decoder circuit
    4.
    发明公开
    Decoder circuit 失效
    解码器电路

    公开(公告)号：EP0031681A3

    公开(公告)日：1982-02-17

    申请号：EP80304586

    申请日：1980-12-18

    申请人： FUJITSU LIMITED

    发明人： Tanaka, Miki ,  Isogai, Hideaki

    IPC分类号： G11C11/40

    CPC分类号： H03K17/62 ,  G11C11/415 ,  G11C11/416 ,  H03M7/005

    摘要： A decoder circuit comprises:
    a differential amplifier circuit 41 which receives one or a plurality of line selection signals B which are to be decoded; switching circuits 31a-1, 31a-2, for switching predetermined line systems 50a, 51a in high or low level states according to the output signal B, B supplied from the differential amplifier circuit 41, and constant current supply circuits 21, 22 for supplying constant current to predetermined lines 13a, 14a of the above line systems 50a, 51a according to the signal supplied from the switching circuits 31a-1, 31a-2. The switching circuits 31a-1, 31a-2 are connected in parallel with respect to the constant current supply circuits 21, 22.

    Switch matrix apparatus for satellite-switched TDMA system or the like
    5.
    发明公开
    Switch matrix apparatus for satellite-switched TDMA system or the like 失效
    Schaltmatrixfürein SS-TDMA-System oder dgl。

    公开(公告)号：EP0033149A2

    公开(公告)日：1981-08-05

    申请号：EP81100511.5

    申请日：1981-01-23

    申请人： NEC CORPORATION

    发明人： Saga, Ryokichi ,  Takimoto, Yukio

    IPC分类号： H04B7/185 ,  H03K17/62 ,  H04N5/22

    CPC分类号： H03K17/62 ,  H04B7/2046 ,  H04Q11/04 ,  H04Q2213/1302 ,  H04Q2213/1304 ,  H04Q2213/13291 ,  H04Q2213/13292 ,  H04Q2213/13306 ,  H04Q2213/13333 ,  Y02D70/446

    摘要： The switch matrix apparatus may be used, for example, in SS-TDMA or FDMA systems in relay stations where a plurality of stations carry on the communications with each other arbitrarily via the relay stations. This switch matrix apparatus (4) comprises M distributing means (201-20M) for distributing an input signal applied thereto into N signals wherein M and N are positive integers; N combining means (301-30N) for combining the respective distributing outputs of said M distributing means (201-20M) to a signal, respectively, said N combining means (301-30N) respectively including a current combining means using resistances and a low input impedance circuit to be connected to the output of said current combining means; and M x N switching circuit means (11 to MN) connected respectively between the outputs of said M distributing means (201-20M) and the inputs of said N combining means (301-30N), said M x N switching circuit means (11 to MN) respectively having a switch means with a high input impedance and a low output impedance. In this switch matrix apparatus the impedance matching among circuits is easily achieved even if there are long connection distances between the circuits; the impedance matching may be unnecessary if the distances are short with small losses caused thereby. Furthermore, the switch matrix apparatus may have high speed, compact, light weight and low power consumption characteristics, and flexibility against the change in the number of the input/output signals.

    摘要翻译： 例如，交换矩阵装置可以用在中继站中的SS-TDMA或FDMA系统中，其中多个站经由中继站任意地进行通信。 该开关矩阵装置（4）包括用于将施加到其上的输入信号分配成N个信号的M个分配装置（201-20M），其中M和N是正整数; N组合装置（301-30N），用于分别将所述M个分配装置（201-20M）的各个分配输出与信号分别组合，所述N个组合装置（301-30N）分别包括使用电阻和低电平的电流组合装置 输入阻抗电路，连接到所述当前组合装置的输出; 以及分别连接在所述M个分配装置（201-20M）的输出端和所述N个组合装置（301-30N）的输入端之间的M×N个切换电路装置（11至MN），所述M×N个切换电路装置 到MN），分别具有高输入阻抗和低输出阻抗的开关装置。 在该开关矩阵装置中，即使在电路之间存在较长的连接距离，也容易实现电路之间的阻抗匹配; 如果距离短而导致由此引起的小损失，则阻抗匹配可能是不必要的。 此外，开关矩阵装置可以具有高速度，紧凑，重量轻和低功耗特性，以及抵抗输入/输出信号数量变化的灵活性。

    Decoder circuit
    6.
    发明公开
    Decoder circuit 失效
    解码器电路

    公开(公告)号：EP0031681A2

    公开(公告)日：1981-07-08

    申请号：EP80304586.3

    申请日：1980-12-18

    申请人： FUJITSU LIMITED

    发明人： Tanaka, Miki ,  Isogai, Hideaki

    IPC分类号： G11C11/40

    CPC分类号： H03K17/62 ,  G11C11/415 ,  G11C11/416 ,  H03M7/005

    摘要： A decoder circuit comprises:

    a differential amplifier circuit 41 which receives one or a plurality of line selection signals B which are to be decoded; switching circuits 31a-1, 31a-2, for switching predetermined line systems 50a, 51a in high or low level states according to the output signal B, B supplied from the differential amplifier circuit 41, and constant current supply circuits 21, 22 for supplying constant current to predetermined lines 13a, 14a of the above line systems 50a, 51a according to the signal supplied from the switching circuits 31a-1, 31a-2. The switching circuits 31a-1, 31a-2 are connected in parallel with respect to the constant current supply circuits 21, 22.

    摘要翻译： 解码器电路包括：差分放大器电路41，其接收要被解码的一个或多个行选择信号B; 用于根据从差分放大器电路41提供的输出信号B，B将预定线路系统50a，51a切换为高电平或低电平状态的开关电路31a-1,31a-2以及用于供应电流的恒定电流供应电路21,22 根据从开关电路31a-1,31a-2提供的信号将恒定电流提供给上述线路系统50a，51a的预定线路13a，14a。 开关电路31a-1,31a-2相对于恒流源电路21,22并联连接。

    VARIABLE LENGTH ARBITRATION
    7.
    发明授权
    VARIABLE LENGTH ARBITRATION 有权

    公开(公告)号：EP2700014B1

    公开(公告)日：2018-06-20

    申请号：EP12773767.4

    申请日：2012-04-18

    申请人： Marvell World Trade Ltd.

    发明人： ZHU, Jun ,  CAO, Joseph Jun ,  LU, Sheng

    IPC分类号： G06F13/14 ,  G06F13/362

    CPC分类号： G06F13/362 ,  G06F12/00 ,  G06F13/14 ,  H03K17/62

    摘要： In one embodiment, a method determines a plurality of categories for requests for a shared resource being shared by a plurality of entities. A request for the resource is received from an entity in the plurality of entities. The method determines a category in the plurality of categories for the received request. If the received request is determined to be in a first category, the method dispatches the received request to a first arbitration scheme configured to determine an arbitration decision in a first time cycle. If the received request is determined to be in a second category, the method dispatches the received request to a second arbitration scheme configured to determine an arbitration decision in a second time cycle of a different length from the first time cycle.

    Switch matrix apparatus for satellite-switched TDMA system or the like
    9.
    发明公开
    Switch matrix apparatus for satellite-switched TDMA system or the like 失效
    用于卫星切换TDMA系统的开关矩阵设备或类似的

    公开(公告)号：EP0033149A3

    公开(公告)日：1981-10-07

    申请号：EP81100511

    申请日：1981-01-23

    申请人： NEC CORPORATION

    发明人： Saga, Ryokichi ,  Takimoto, Yukio

    IPC分类号： H04B07/185 ,  H04J03/04

    CPC分类号： H03K17/62 ,  H04B7/2046 ,  H04Q11/04 ,  H04Q2213/1302 ,  H04Q2213/1304 ,  H04Q2213/13291 ,  H04Q2213/13292 ,  H04Q2213/13306 ,  H04Q2213/13333 ,  Y02D70/446

    摘要： The switch matrix apparatus may be used, for example, in SS-TDMA or FDMA systems in relay stations where a plurality of stations carry on the communications with each other arbitrarily via the relay stations. This switch matrix apparatus (4) comprises M distributing means (201-20M) for distributing an input signal applied thereto into N signals wherein M and N are positive integers; N combining means (301-30N) for combining the respective distributing outputs of said M distributing means (201-20M) to a signal, respectively, said N combining means (301-30N) respectively including a current combining means using resistances and a low input impedance circuit to be connected to the output of said current combining means; and M x N switching circuit means (11 to MN) connected respectively between the outputs of said M distributing means (201-20M) and the inputs of said N combining means (301-30N), said M x N switching circuit means (11 to MN) respectively having a switch means with a high input impedance and a low output impedance. In this switch matrix apparatus the impedance matching among circuits is easily achieved even if there are long connection distances between the circuits; the impedance matching may be unnecessary if the distances are short with small losses caused thereby. Furthermore, the switch matrix apparatus may have high speed, compact, light weight and low power consumption characteristics, and flexibility against the change in the number of the input/output signals.

    摘要翻译： 例如，交换矩阵装置可以用在中继站中的SS-TDMA或FDMA系统中，其中多个站经由中继站任意地进行通信。 该开关矩阵装置（4）包括用于将施加到其上的输入信号分配成N个信号的M个分配装置（201-20M），其中M和N是正整数; N组合装置（301-30N），用于分别将所述M个分配装置（201-20M）的各个分配输出与信号分别组合，所述N个组合装置（301-30N）分别包括使用电阻和低电平的电流组合装置 输入阻抗电路，连接到所述当前组合装置的输出; 以及分别连接在所述M个分配装置（201-20M）的输出端和所述N个组合装置（301-30N）的输入端之间的M×N个切换电路装置（11至MN），所述M×N个切换电路装置 到MN），分别具有高输入阻抗和低输出阻抗的开关装置。 在该开关矩阵装置中，即使在电路之间存在较长的连接距离，也容易实现电路之间的阻抗匹配; 如果距离短而导致由此引起的小损失，则阻抗匹配可能是不必要的。 此外，开关矩阵装置可以具有高速度，紧凑，重量轻和低功耗特性，以及抵抗输入/输出信号数量变化的灵活性。

    VARIABLE LENGTH ARBITRATION
    10.
    发明公开
    VARIABLE LENGTH ARBITRATION 有权
    可变长度评估

    公开(公告)号：EP2700014A4

    公开(公告)日：2014-10-01

    申请号：EP12773767

    申请日：2012-04-18

    申请人： MARVELL WORLD TRADE LTD

    发明人： ZHU JUN ,  CAO JOSEPH JUN ,  LU SHENG

    IPC分类号： G06F13/14 ,  G06F13/362

    CPC分类号： G06F13/362 ,  G06F12/00 ,  G06F13/14 ,  H03K17/62

    摘要： In one embodiment, a method determines a plurality of categories for requests for a shared resource being shared by a plurality of entities. A request for the resource is received from an entity in the plurality of entities. The method determines a category in the plurality of categories for the received request. If the received request is determined to be in a first category, the method dispatches the received request to a first arbitration scheme configured to determine an arbitration decision in a first time cycle. If the received request is determined to be in a second category, the method dispatches the received request to a second arbitration scheme configured to determine an arbitration decision in a second time cycle of a different length from the first time cycle.