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23 条记录 (耗时 0.009 秒)

    AN INTERRUPTIBLE VOLTAGE-CONTROLLED OSCILLATOR
    1.
    发明授权
    AN INTERRUPTIBLE VOLTAGE-CONTROLLED OSCILLATOR 失效
    一个中断电压控制振荡器

    公开(公告)号：EP0151633B1

    公开(公告)日：1991-04-17

    申请号：EP84903136.4

    申请日：1984-08-03

    申请人： ADVANCED MICRO DEVICES, INC.

    发明人： CAMPBELL, David, L.

    IPC分类号： H03B5/02 ,  H03B5/24 ,  H03K3/03 ,  H03K4/08 ,  H03K4/50 ,  H03K4/94 ,  H03K5/06 ,  H03K6/04 ,  H03K19/086 ,  H03L7/08 ,  H04L7/02

    CPC分类号： H03K3/0315 ,  H03K3/70 ,  H03K9/06 ,  H03K2005/00097 ,  H03K2005/00176 ,  H03L7/07 ,  H03L7/0995 ,  Y10S331/03

    摘要： As shown in (Fig. 2A), the fall time of an ECL gate (20) is precisely controlled using a fixed capacitor (46) which is connected between the positive supply voltage and the ECL gate output terminal (44), and a variable current source (48, 50, 52) connected between ground (GRND 3) and the ECL gate output terminal (44). A time-delay circuit is obtained by controlling the variable current source with an error voltage (VR2) of a phase-locked loop such that the time-delay precisely tracks the frequency of the reference signal for the phase-locked loop. A signal detector circuit is obtained by combining time-delay circuits. A voltage-controlled oscillator is assembled by connecting 3 ECL gates (12, 14, 16), as shown Fig. 1, with controlled fall times in a ring oscillator configuration. Addition of a noninverting input (19) to one ECL gate (16) makes the voltage-controlled oscillator interruptible. Combining a voltage-controlled oscillator of the type described with a phase detector fed by a reference signal provides a phase-locked loop with the control voltage thereof providing a frequency-to-voltage conversion function. A system for providing a receiver clock reference signal from a received signal is provided, as shown in Figs. 5A and 5B, by phase-locking the output signal of a first phase-locked loop (130) to a system reference signal (TCK) to generate a first-loop control voltage (X4). A second phase-locked loop is phase-locked to the received signal (MNCK) with a second-loop control voltage (VR4). In addition, the second phase-locked loop (142) is also frequency-locked to the system reference signal (TCK) by the first-loop control voltage (X4). This system is particularly useful for recovering a receiver clock reference from a Manchester-encoded signal.

    Radar oscillator capable of preventing leak of oscillation output
    3.
    发明公开
    Radar oscillator capable of preventing leak of oscillation output 审中-公开
    Radaroszillator mit derFähigkeitzum Verhindern eines Lecks bei der Oszillationsausgabe

    公开(公告)号：EP2698645A2

    公开(公告)日：2014-02-19

    申请号：EP13185864.9

    申请日：2005-05-23

    申请人： ANRITSU CORPORATION ,  Panasonic Corporation

    发明人： Arayashiki, Yutaka ,  Saito, Sumio ,  Ejima, Masanori

    IPC分类号： G01S7/03 ,  G01S7/282 ,  H03K3/70

    CPC分类号： G01S7/282 ,  G01S7/03 ,  H03B5/1203 ,  H03B5/1215 ,  H03B5/1221 ,  H03B5/1231 ,  H03K3/70

    摘要： The present invention, in order to enable intermittent output of an oscillation signal without essentially producing a leak in response to a pulse signal indicating a transmission timing of a radar wave, employs a configuration in which an operation of an oscillating unit (21) itself of a radar oscillator is alternately changed between an oscillating state and an oscillation stop state by a switch (30), not a configuration in which an output passage of an oscillation signal is switched to be opened and closed as in a conventional radar oscillator.

    摘要翻译： 本发明为了能够根据表示雷达波的发送定时的脉冲信号基本上产生泄漏而能够间歇地输出振荡信号，采用这样的结构，其中振荡单元（21）本身的操作 雷达振荡器通过开关（30）在振荡状态和振荡停止状态之间交替地变化，而不是如常规雷达振荡器那样将振荡信号的输出通道切换为打开和关闭的结构。

    A programmable oscillator with power down feature and frequency adjustment
    5.
    发明公开
    A programmable oscillator with power down feature and frequency adjustment 失效
    可编程振荡器与去激活功能和频率调整。

    公开(公告)号：EP0144636A1

    公开(公告)日：1985-06-19

    申请号：EP84112376.3

    申请日：1984-10-16

    申请人： International Business Machines Corporation

    发明人： Cranford, Hayden, Jr. ,  Garvin, Stacy Jean

    IPC分类号： H03K3/354

    CPC分类号： H03K3/354 ,  H03K3/0315 ,  H03K3/70

    摘要： A programmable oscillator (18) is provided for use on an integrated circuit chip. The oscillator (18) includes a plurality of inverted delay stages (80, 82, ...) connected in tandem between an input (INPUT) and an output node (Z). A single FET device (39) couples a common node (X) to a ground potential. Another FET device (31) controls the control node G. When a logic enabling signal is appropriately applied to the FET devices, the oscillator (18) is controlled so that internal nodes (G, H, ...) of the oscillator float high when it is off and no energy is dissipated. In addition, the ratio of delays between the delay stages (80, 82, ...) and the input stage (92) of the load (37) is such that the load (37) supplies the greater ratio of delays. This ensures that the oscillator's frequency of oscillation tracks the switching speed of the load (37).

    A glitch free controlled ring oscillator
    6.
    发明公开
    A glitch free controlled ring oscillator 审中-公开
    失败的自由干控制环形振荡器

    公开(公告)号：EP1672791A3

    公开(公告)日：2008-09-17

    申请号：EP05112285.1

    申请日：2005-12-16

    申请人： STMicroelectronics Pvt. Ltd

    发明人： Tiwari, Naveen ,  Singh, Balwant

    IPC分类号： H03K3/03

    CPC分类号： G06F1/04 ,  H03K3/0315 ,  H03K3/70

    摘要： A glitch free controlled ring oscillator comprising a programmable delay chain (1) connected to a gating and inverting means (3) wherein a latching means (2) is provided between said prgrammable delay chain (1) and said gating and inverting means (3) for registering the clock state at the time of disabling the oscillator and setting the output of the oscillator to said registered clock state.

    A glitch free controlled ring oscillator
    7.
    发明公开
    A glitch free controlled ring oscillator 审中-公开
    Eine fehlimpulsfreier gesteuerter Ringoszillator

    公开(公告)号：EP1672791A2

    公开(公告)日：2006-06-21

    申请号：EP05112285.1

    申请日：2005-12-16

    申请人： STMicroelectronics Pvt. Ltd

    发明人： Tiwari, Naveen ,  Singh, Balwant

    IPC分类号： H03K3/03

    CPC分类号： G06F1/04 ,  H03K3/0315 ,  H03K3/70

    摘要： A glitch free controlled ring oscillator comprising a programmable delay chain connected to a gating and inverting means wherein a latching means is provided between said delay chain and said gating and inverting means for registering the clock state at the time of disabling the oscillator and setting the output of the oscillator to said registered clock state.

    摘要翻译： 一种无毛刺控制环形振荡器，包括连接到门控和反相装置（3）的可编程延迟链（1），其中在所述可编程延迟链（1）和所述选通和反相装置（3）之间提供锁存装置（2） 用于在禁止振荡器并将振荡器的输出设置为所述注册的时钟状态时注册时钟状态。

    AN INTERRUPTIBLE VOLTAGE-CONTROLLED OSCILLATOR.
    9.
    发明公开
    AN INTERRUPTIBLE VOLTAGE-CONTROLLED OSCILLATOR. 失效
    中断压控振荡器。

    公开(公告)号：EP0151633A4

    公开(公告)日：1987-04-28

    申请号：EP84903136

    申请日：1984-08-03

    申请人： ADVANCED MICRO DEVICES INC

    发明人： CAMPBELL DAVID L

    IPC分类号： H03B5/02 ,  G01R29/02 ,  H03K3/03 ,  H03K3/282 ,  H03K3/70 ,  H03K5/00 ,  H03K9/06 ,  H03K19/086 ,  H03L7/07 ,  H03L7/08 ,  H03L7/099 ,  H03M5/12 ,  H04L25/49

    CPC分类号： H03K3/0315 ,  H03K3/70 ,  H03K9/06 ,  H03K2005/00097 ,  H03K2005/00176 ,  H03L7/07 ,  H03L7/0995 ,  Y10S331/03

    摘要： As shown in (Fig. 2A), the fall time of an ECL gate (20) is precisely controlled using a fixed capacitor (46) which is connected between the positive supply voltage and the ECL gate output terminal (44), and a variable current source (48, 50, 52) connected between ground (GRND 3) and the ECL gate output terminal (44). A time-delay circuit is obtained by controlling the variable current source with an error voltage (VR2) of a phase-locked loop such that the time-delay precisely tracks the frequency of the reference signal for the phase-locked loop. A signal detector circuit is obtained by combining time-delay circuits. A voltage-controlled oscillator is assembled by connecting 3 ECL gates (12, 14, 16), as shown Fig. 1, with controlled fall times in a ring oscillator configuration. Addition of a noninverting input (19) to one ECL gate (16) makes the voltage-controlled oscillator interruptible. Combining a voltage-controlled oscillator of the type described with a phase detector fed by a reference signal provides a phase-locked loop with the control voltage thereof providing a frequency-to-voltage conversion function. A system for providing a receiver clock reference signal from a received signal is provided, as shown in Figs. 5A and 5B, by phase-locking the output signal of a first phase-locked loop (130) to a system reference signal (TCK) to generate a first-loop control voltage (X4). A second phase-locked loop is phase-locked to the received signal (MNCK) with a second-loop control voltage (VR4). In addition, the second phase-locked loop (142) is also frequency-locked to the system reference signal (TCK) by the first-loop control voltage (X4). This system is particularly useful for recovering a receiver clock reference from a Manchester-encoded signal.

    Clock signal generator for start-stop operation
    10.
    发明公开
    Clock signal generator for start-stop operation 失效
    用于启停操作的时钟信号发生器

    公开(公告)号：EP0071978A3

    公开(公告)日：1985-07-10

    申请号：EP82107052

    申请日：1982-08-04

    申请人： Siemens Aktiengesellschaft

    发明人： Urbigkeit, Frank, Ing, grad.

    IPC分类号： H03K03/70 ,  H03K03/017

    CPC分类号： H03K3/017 ,  H03K3/70

    摘要： Die Erfindung betrifft einen Taktgenerator für Start- Stop-Betrieb mit wählbarem Impuls-Pausenverhältnis. Das Grundelement des Taktgenerators ist ein bandfilter gekoppelter Oszillator mit zwei invertierenden Ver knüpfungsgliedern, der zur Erhöhung der Frequenzkon stanz durch einen Quarzoszillator synchronisiert wird. Zur Verbesserung der Konstanz der Impulslängen von Taktimpulsen, die kürzer als eine halbe Taktperiode sind, ist ein zusätzlicher quarzgesteuerter Führungsoszillator vorgesehen.