公开(公告)号：EP2211464A1

公开(公告)日：2010-07-28

申请号：EP09151322.6

申请日：2009-01-26

申请人： Siemens Aktiengesellschaft

发明人： Beyer, Stefan

IPC分类号： H03K6/04 ,  H03K5/06 ,  H03K17/16 ,  H03K19/003

CPC分类号： H03K6/04 ,  H03K5/06 ,  H03K17/166 ,  H03K19/00361

摘要： Die Erfindung betrifft eine Schaltung zur Generierung von Rechteckimpulsfolgen als Sendesignal für eine Kommunikationsleitung welche Rechteckimpulsfolgen mit guten Flanken und guter elektromagnetischer Verträglichkeit generieren. Hierbei wird vorgeschlagen, dass die Schaltung umfasst:
- ein erstes Element, zum Schalten eines High Pegels auf der Kommunikationsleitung,
- ein zweites Element, zum Schalten eines Low Pegels auf der Kommunikationsleitung,
- eine Verarbeitungseinheit, welche durch Ansteuerung des ersten und zweiten Elements die Rechteckimpulsfolgen auf der Kommunikationsleitung erzeugen kann, und Empfangsmittel zum Empfangen von zur Schaltung gesandten Rechteckimpulsfolgen auf der Kommunikationsleitung aufweist,

wobei die Verarbeitungseinheit dazu eingerichtet ist, bei einer Schaltung eines Pegelwechsels von High Pegel auf Low Pegel oder von Low Pegel auf High Pegel mittels der Empfangsmittel einen die Flankensteigung des Pegelwechsels charakterisierenden Wert zu ermitteln und anhand des ermittelten Wertes das erste Element und/oder das zweite Element dahingehend einzustellen, dass bei einer erneuten Schaltung des Pegelwechsels eine erwünschte Flankensteigung auf der Kommunikationsleitung erreicht wird.

摘要翻译： 开关（1）具有分别用于切换通信电缆（2）的高电平和低电平的开关元件（6,7）。 在通过接收单元切换电平改变期间，处理单元（5），即通用异步接收机发射机，将表征电平变化的边沿梯度的值从高电平确定为低电平或从低电平确定为高电平。 处理单元基于确定的值调整开关元件的电阻，使得在切换电平变化期间在电缆上获得期望的边缘梯度。 还包括用于生成矩形脉冲串作为通信电缆的发送信号的方法的独立权利要求。

公开(公告)号：EP1537650A4

公开(公告)日：2010-06-09

申请号：EP03765803

申请日：2003-07-18

申请人： INTERDIGITAL TECH CORP

发明人： KWAK JAEYOUNG ,  PAN JUNG-LIN ,  ZEIRA ARIELA

IPC分类号： H04B1/707 ,  H04B7/04 ,  H04B7/08 ,  H04L1/06 ,  H04L25/02 ,  H04L25/03 ,  H03D1/04 ,  H03D1/06 ,  H03K5/01 ,  H03K6/04 ,  H04B1/10 ,  H04L1/00 ,  H04L25/08

CPC分类号： H04B1/71055 ,  H04B1/7093 ,  H04B1/71072 ,  H04B7/0854 ,  H04L1/06 ,  H04L25/0212 ,  H04L25/0226 ,  H04L25/03305 ,  H04L25/03318

公开(公告)号：EP1177618A1

公开(公告)日：2002-02-06

申请号：EP00916379.1

申请日：2000-03-15

申请人： Sapphire Communications, Inc.

发明人： TRANS, François ,  LE-NGOC, Tho

IPC分类号： H03D1/04 ,  H03D1/06 ,  H03K5/01 ,  H03K6/04 ,  H04B1/10 ,  H04L1/00 ,  H04L25/08

CPC分类号： H04B3/32 ,  H04J3/0638 ,  H04L7/0008 ,  H04L25/03038 ,  H04L2025/03363 ,  H04L2025/0349 ,  H04L2025/03509

摘要： In a bidirectional data chanel between a central station and a multiple of remote stations, a method (fig. 6) for equalizing interference over a synchronized packet or frame based baseband transmission system wherein the crosstalk on the system is cyclostationary or periodic with a period equal to a symbol interval, the method (fig. 6) comprising the steps of synchronizing the trannsmitters and receivers using the uncorrelated transmit signals; generating the cyclostationary NEXT and FEXT interference (fig. 6) along with ISI using the uncorrelated symbols at the synchronized transmitters at one or more remote stations and the centrally station; using cascaded fractionally spaced linear equalizer (FSLE) and decision feedback equalizer (DFE) for both interference supression and equalization to minimize excess bandwidth at central receivers at the central station; (fig. 6) increasing the receiver's FSLE filter taps (NT) to maximize signal to noise ratio; (fig. 6) combining FSLE/DFE and proper phase sampling adjustment, enabling use of the spectral correlation properties peculiar to the modified signals (fig. 6).

公开(公告)号：EP0711037A3

公开(公告)日：1997-06-11

申请号：EP95307814.4

申请日：1995-11-01

申请人： SYMBIOS LOGIC INC.

发明人： Rehm, Dennis J. ,  Callahan, Phillip A.

IPC分类号： H03K5/24 ,  H03K3/011 ,  H03K6/04

CPC分类号： H03K17/145 ,  H03K5/082 ,  H03K5/2481 ,  H03K17/163 ,  H03K17/164

摘要： The invention provides for a signal generator and related method of signal generator that is tolerant to supply voltage fluctuations and differentials. A current switch (10) is arranged to be driven and that is independent of the supply voltage. By clamping the slewing voltage at the gate of a transistor driver (M5, M6), the difference between the clamped gate voltage and the threshold turn on voltage of the driver (M5,M6) is constant with respect to the supply voltage. This causes the transition edges of the driver's output voltage to be constant with respect to the supply voltage. This technique minimizes variations in the output signal edge transitions as the supply voltage varies overvarious tolerance ranges. Because this technique increases the control of the transition edges in the output signal, it is possible to generate much slower edges and still maintain a consistent transition voltage shape with variations in the supply voltage and the symbol width.

公开(公告)号：EP0711037A2

公开(公告)日：1996-05-08

申请号：EP95307814.4

申请日：1995-11-01

申请人： SYMBIOS LOGIC INC.

发明人： Rehm, Dennis J. ,  Callahan, Phillip A.

IPC分类号： H03K5/24 ,  H03K3/011 ,  H03K6/04

CPC分类号： H03K17/145 ,  H03K5/082 ,  H03K5/2481 ,  H03K17/163 ,  H03K17/164

摘要： The invention provides for a signal generator and related method of signal generator that is tolerant to supply voltage fluctuations and differentials. A current switch (10) is arranged to be driven and that is independent of the supply voltage. By clamping the slewing voltage at the gate of a transistor driver (M5, M6), the difference between the clamped gate voltage and the threshold turn on voltage of the driver (M5,M6) is constant with respect to the supply voltage. This causes the transition edges of the driver's output voltage to be constant with respect to the supply voltage. This technique minimizes variations in the output signal edge transitions as the supply voltage varies over various tolerance ranges. Because this technique increases the control of the transition edges in the output signal, it is possible to generate much slower edges and still maintain a consistent transition voltage shape with variations in the supply voltage and the symbol width.

摘要翻译： 本发明提供信号发生器和信号发生器的相关方法，其容忍电压波动和差动。 电流开关（10）被布置成被驱动，并且与电源电压无关。 通过将晶体管驱动器（M5，M6）的栅极上的回转电压钳位，钳位的栅极电压与驱动器（M5，M6）的阈值导通电压之间的差值相对于电源电压是恒定的。 这导致驱动器的输出电压的过渡边缘相对于电源电压是恒定的。 当电源电压在各种公差范围内变化时，该技术可以最大限度地减小输出信号边沿转换的变化。 由于这种技术可以增加输出信号中过渡边沿的控制，所以可以产生较慢的边沿，并且仍然保持一致的过渡电压形状，随着电源电压和符号宽度的变化。

公开(公告)号：EP0390356A3

公开(公告)日：1991-09-25

申请号：EP90302482.6

申请日：1990-03-08

申请人： NOKIA MOBILE PHONES LTD.

发明人： Vaisanen, Risto ,  Pekkarinen, Vesa ,  Sarasmo, Jukka

IPC分类号： H03K6/04

CPC分类号： H03K4/94 ,  G06G7/22 ,  H03K6/04

摘要： The invention relates to the forming of a control pulse, for the transmitter in a GSM radio telephone system. A cos² pulse is formed by means of an analog circuit from a rectangular pulse which is first shaped into a triangular pulse which may be somewhat clipped at its peak. The triangular pulse is further shaped into a cos² pulse. The circuit also includes means (Cr...CN; R14...RN; Q7...QN) by using which the abruptness of the triangular pulse and thereby the abruptness of the cos² pulse can be selected.

公开(公告)号：EP0151633B1

公开(公告)日：1991-04-17

申请号：EP84903136.4

申请日：1984-08-03

申请人： ADVANCED MICRO DEVICES, INC.

发明人： CAMPBELL, David, L.

IPC分类号： H03B5/02 ,  H03B5/24 ,  H03K3/03 ,  H03K4/08 ,  H03K4/50 ,  H03K4/94 ,  H03K5/06 ,  H03K6/04 ,  H03K19/086 ,  H03L7/08 ,  H04L7/02

CPC分类号： H03K3/0315 ,  H03K3/70 ,  H03K9/06 ,  H03K2005/00097 ,  H03K2005/00176 ,  H03L7/07 ,  H03L7/0995 ,  Y10S331/03

摘要： As shown in (Fig. 2A), the fall time of an ECL gate (20) is precisely controlled using a fixed capacitor (46) which is connected between the positive supply voltage and the ECL gate output terminal (44), and a variable current source (48, 50, 52) connected between ground (GRND 3) and the ECL gate output terminal (44). A time-delay circuit is obtained by controlling the variable current source with an error voltage (VR2) of a phase-locked loop such that the time-delay precisely tracks the frequency of the reference signal for the phase-locked loop. A signal detector circuit is obtained by combining time-delay circuits. A voltage-controlled oscillator is assembled by connecting 3 ECL gates (12, 14, 16), as shown Fig. 1, with controlled fall times in a ring oscillator configuration. Addition of a noninverting input (19) to one ECL gate (16) makes the voltage-controlled oscillator interruptible. Combining a voltage-controlled oscillator of the type described with a phase detector fed by a reference signal provides a phase-locked loop with the control voltage thereof providing a frequency-to-voltage conversion function. A system for providing a receiver clock reference signal from a received signal is provided, as shown in Figs. 5A and 5B, by phase-locking the output signal of a first phase-locked loop (130) to a system reference signal (TCK) to generate a first-loop control voltage (X4). A second phase-locked loop is phase-locked to the received signal (MNCK) with a second-loop control voltage (VR4). In addition, the second phase-locked loop (142) is also frequency-locked to the system reference signal (TCK) by the first-loop control voltage (X4). This system is particularly useful for recovering a receiver clock reference from a Manchester-encoded signal.

公开(公告)号：EP0390562A2

公开(公告)日：1990-10-03

申请号：EP90303367.8

申请日：1990-03-29

申请人： Hewlett-Packard Company

发明人： Chism, Wayne R. ,  King, Philip N.

IPC分类号： H03K4/00 ,  H03K6/04 ,  G01R31/318

CPC分类号： G01R31/31924 ,  H03K5/12

摘要： A method and apparatus for providing pulse signals from a driver circuit (10) in an in-circuit overdrive/functional tester to a probe (25), which tester provides a control signal representative of a command for the driver circuit to provide logic signals, includes adjusting the transition time of the logic signals so that the transition time is equal to twice the time it takes the pulse signal to travel from the driver circuit (10) to the end of the probe (25) and back. The method or apparatus for adjusting the rise time of the control signal can include adjusting the slew rate of the control signal. Pulse signals produced by such a method or apparatus have clean edges, have slew rates which are twice as fast as the slew rates of the driver signals and have zero propagation delay when measured at the fifty percent point.

摘要翻译： 一种用于将来自在线过载/功能测试仪中的驱动器电路（10）的脉冲信号提供给探头（25）的方法和装置，该测试器提供表示驱动器电路提供逻辑信号的命令的控制信号， 包括调整逻辑信号的转换时间，使得转换时间等于脉冲信号从驱动器电路（10）行进到探头（25）的端部所需的时间的两倍。 用于调整控制信号的上升时间的方法或装置可以包括调整控制信号的转换速率。 由这种方法或装置产生的脉冲信号具有干净的边缘，其转换速率是驱动器信号的转换速度的两倍，并且在百分之五点测量时具有零传播延迟。

公开(公告)号：EP0282981A3

公开(公告)日：1989-10-18

申请号：EP88104128.9

申请日：1988-03-15

申请人： SGS Halbleiter-Bauelemente GmbH

发明人： Reichmeyer, Hans ,  Stockinger, Josef

IPC分类号： H03K5/02 ,  H03K6/04 ,  H03K17/16

CPC分类号： H03K17/6872 ,  H03K17/163 ,  H03K17/166 ,  H03K19/0013

摘要： Digitale-Gegentakt-Treiberschaltung mit zwei von einer Daten-Steuerschaltung abwechselnd leitend gesteuerten Ausgangstransistoren (Q₁, Q₂), an deren gemeinsamen Verbindungs­punkt (O) eine zu treibende Last angeschlossen ist. Zwischen die Steuerelektrode eines jeden der beiden Ausgangs­transistoren (Q₁, Q₂) und die Daten-Steuerschaltung ist je eine flankensteilheitsvermindernde, freigabeabhängige Ver­zögerungsschaltung (V₁, V₂) geschaltet. Dabei ist der Ausgang einer jeden Verzögerungsschaltung (V₁, V₂) mit einem Freigabe­eingang der jeweils anderen Verzögerungsschaltung (V₂, V₁) ver­bunden. Die Verzögerungszeiten der beiden Verzögerungs­glieder (V₁, V₂) sind mindestens so lang wie die zeitliche Breite der steilheitsverminderten Impulsflanken.

公开(公告)号：EP0094431A4

公开(公告)日：1987-11-30

申请号：EP83900369

申请日：1982-11-05

申请人： GOULD INC

发明人： HARRIS ROBERT W

IPC分类号： H04L25/52 ,  G08C15/00 ,  H04B1/74 ,  H04B3/36 ,  H04B3/44 ,  H04B10/29 ,  H04L7/00 ,  H04L7/04 ,  H04L7/10 ,  H04L12/40 ,  H04L25/24 ,  H02M3/28 ,  H03K6/02 ,  H03K6/04

CPC分类号： H04L12/4035 ,  G08C15/00 ,  H04B1/74 ,  H04B1/745 ,  H04B3/36 ,  H04B3/44 ,  H04B10/29 ,  H04L7/0083 ,  H04L7/04 ,  H04L7/044 ,  H04L7/10 ,  H04L12/40032 ,  H04L25/24

摘要： A telemetry system for sensing remote physical events and for transmitting and boosting a digital data signal representing the sensed events on a transmission line (22), which comprises a master clock (24, 26) and a plurality of sensing stations (20) for sensing local data. The sensing stations (20) inject local data onto the transmission line (22) as a digital data signal, and a controller/receiver (28) receives the digital data. The master clock (24, 26) initializes the system timing and generates a sync signal. Each sensing station (20) includes a booster subsystem (40) for receiving the local digital data and for injecting the digital data onto the transmission line (22) as a digital data signal. During system start-up, each booster subsystem (40) claims a slot, in accordance with an organizational process, for injecting the digital data signal onto the transmission line (22). The booster subsystem (40) in each sensing station (20) further includes a booster circuit (60) for boosting the digital data signals which are propagating on the transmission line (22), as well as the sync signal. The booster circuit (60) comprises a negative impedance bistable device for enhancing the amplitude and rise time of the digital data signal. Each booster subsystem (40) further includes a switching mode regulator circuit (56) for converting a supply current on the transmission line (22) to a level voltage, thereby providing local power to the components of the sensing station (20).