Abstract:
Systems and methods for insuring successful initiation of a resonating micro-electro mechanical systems (MEMS). An example system (20) includes a resonating sensor (24), a drive device (26), a charge amplifier, and a voltage gain circuit (28). At start up, the charge amplifier and voltage gain circuit receives signals from the resonating sensor, compensates this signal for DC offsets, and generates a clock signal for the drive, thus placing the resonating sensor in a steady state operating mode. The circuit includes a plurality of switches that are toggled to produce a glitch in the signal associated with the received signal. The glitch overcomes the DC offset. A comparator generates the clock signal for the drive device if a signal associated with the received signal exceeds a reference signal.
Abstract:
The circuit arrangement (1) comprises an input (2) for connecting an oscillator (3) and an amplifier circuit (20) having a first input (21), which is coupled to the input (2) of the circuit arrangement (1), having a second input (22) and having an output (23), which is connected to an output (4) of the circuit arrangement (1). A clock signal (Vout) with a duty ratio (j) can be tapped off at the output (4) of the circuit arrangement (1). Furthermore, the circuit arrangement (1) has a low-pass filter (40), which is connected on the input side to the output (23) of the amplifier circuit (20), and an integrator circuit (50), which is connected on the input side to the low-pass filter (40) and on the output side to the second input (22) of the amplifier circuit (20) for the purpose of outputting a predeterminable threshold value (Vth) for controlling the duty ratio factor (j).
Abstract:
A common-mode voltage controller for adjusting common-mode voltages between a first buffer and a second buffer at a subsequent stage or a preceding stage of the first buffer in a signal transmission circuit, comprising: a first reference voltage generation unit for generating a common-mode voltage corresponding to the first buffer; a second reference voltage generation unit for generating a common-mode voltage corresponding to the second buffer at the subsequent stage or the preceding stage; and a control signal generation unit for generating a control signal for controlling a common-mode voltage of the first buffer according to a difference voltage between an output of the first reference voltage generation unit and an output of the second reference voltage generation unit, and giving the control signal to the first buffer and first reference voltage generation unit.
Abstract:
In a circuit (1) for producing or transmitting control signals (Q) for a current inverter (2) comprising at least one first switch (Shigh) with a high potential and a second switch (Slow) with a low potential, a connection point between the two switches (Shigh, Slow) forms the output of the current inverter (2). The circuit (1) also comprises a capacitor (Ccap) which a) is connected to the output of the current inverter (2) in a first operating phase by means of switching elements (S1-S4), in such a way that it enables a current flow in a state wherein the two switches (Shigh/ Slow) of the current inverter (2) are open, and b) is connected to the current inverter output in a second operating phase by means of the switching elements (S1-S4) with high impedance, such that a control signal (Q) applied to a side of the capacitor (Ccap) by a control device is transformed into a higher potential.
Abstract:
A low power consumption shift register which inputs a CK signal with a low voltage with almost no effect of variation in characteristics of transistors. In the invention, an input portion of an inverter is set at a threshold voltage thereof and a CK signal is inputted to the input portion of the inverter through a capacitor means. In this manner, the CK signal is amplified, which is sent to the shift register. That is, by obtaining the threshold potential of the inverter, the shift register which operates with almost no effect of variation in characteristics of transistors can be provided.
Abstract:
An improved data receiver gain enhancement is obtained in circuit by having a V/I converter and an amplifier stage, by placing a passive filter between in converter and amplifier stage. Amplification of certain parts of the signal, more than other parts can be obtained, depending on the characteristics of the filter.
Abstract:
The invention relates to a burst receiver for receiving an optical burst-mode signal (1), comprising signals with different power levels, originating from different senders. The burst receiver (10) comprises first conversion means (13, 14), that are arranged for receiving the input signal (1) and providing an inverted and a non-inverted optical signal (5, 4). These inverted and non-inverted optical signals (5, 4) are applied to a balanced receiver (6). The balanced receiver (10) provides an electrical output signal (9) corresponding to the difference between the inverted and non-inverted optical signal (5, 4).