Systems and methods to overcome DC offsets in amplifiers used to start resonant micro-electro mechanical systems
    4.
    发明公开
    Systems and methods to overcome DC offsets in amplifiers used to start resonant micro-electro mechanical systems 审中-公开
    其用于谐振微型电动机械系统的起动在放大器克服德克·德利的系统和方法

    公开(公告)号:EP2178208A2

    公开(公告)日:2010-04-21

    申请号:EP09172605.9

    申请日:2009-10-08

    Inventor: Suttor, Michael

    Abstract: Systems and methods for insuring successful initiation of a resonating micro-electro mechanical systems (MEMS). An example system (20) includes a resonating sensor (24), a drive device (26), a charge amplifier, and a voltage gain circuit (28). At start up, the charge amplifier and voltage gain circuit receives signals from the resonating sensor, compensates this signal for DC offsets, and generates a clock signal for the drive, thus placing the resonating sensor in a steady state operating mode. The circuit includes a plurality of switches that are toggled to produce a glitch in the signal associated with the received signal. The glitch overcomes the DC offset. A comparator generates the clock signal for the drive device if a signal associated with the received signal exceeds a reference signal.

    Abstract translation: 系统和用于确保谐振微机电系统(MEMS)的成功启动方法。 的示例性系统(20)包括谐振传感器(24),驱动装置(26),一个电荷放大器和电压增益电路(28)。 在启动时,电荷放大器和电压增益电路从所述共振传感器的驱动器接收信号,该补偿信号对DC偏移,和基因率的时钟信号,从而将共振传感器在稳定状态的操作模式。 该电路包括开关的多元性没被切换以产生与接收到的信号相关联的信号中的假信号。 毛刺在谈到直流偏移。 如果与接收到的信号相关联的信号超过参考信号的比较基因我们获得了驱动装置的时钟信号。

    SCHALTUNGSANORDNUNG UND VERFAHREN ZUM BEREITSTELLEN EINES TAKTSIGNALS MIT EINEM EINSTELLBAREN TASTVERHÄLTNIS
    5.
    发明授权
    SCHALTUNGSANORDNUNG UND VERFAHREN ZUM BEREITSTELLEN EINES TAKTSIGNALS MIT EINEM EINSTELLBAREN TASTVERHÄLTNIS 有权
    电路装置和方法提供时钟信号与占空比可调

    公开(公告)号:EP1997227B1

    公开(公告)日:2009-07-22

    申请号:EP07723219.7

    申请日:2007-03-13

    Inventor: DENIER, Urs

    CPC classification number: H03K5/1565 H03K5/003 H03K5/08

    Abstract: The circuit arrangement (1) comprises an input (2) for connecting an oscillator (3) and an amplifier circuit (20) having a first input (21), which is coupled to the input (2) of the circuit arrangement (1), having a second input (22) and having an output (23), which is connected to an output (4) of the circuit arrangement (1). A clock signal (Vout) with a duty ratio (j) can be tapped off at the output (4) of the circuit arrangement (1). Furthermore, the circuit arrangement (1) has a low-pass filter (40), which is connected on the input side to the output (23) of the amplifier circuit (20), and an integrator circuit (50), which is connected on the input side to the low-pass filter (40) and on the output side to the second input (22) of the amplifier circuit (20) for the purpose of outputting a predeterminable threshold value (Vth) for controlling the duty ratio factor (j).

    COMMON-MODE VOLTAGE CONTROLLER
    6.
    发明公开
    COMMON-MODE VOLTAGE CONTROLLER 有权
    GLEICHTAKTSPANNUNGSSTEUERUNG

    公开(公告)号:EP1926214A1

    公开(公告)日:2008-05-28

    申请号:EP05783491.3

    申请日:2005-09-16

    CPC classification number: H04L25/0276 H03K5/003 H03K19/017545 H04L25/028

    Abstract: A common-mode voltage controller for adjusting common-mode voltages between a first buffer and a second buffer at a subsequent stage or a preceding stage of the first buffer in a signal transmission circuit, comprising: a first reference voltage generation unit for generating a common-mode voltage corresponding to the first buffer; a second reference voltage generation unit for generating a common-mode voltage corresponding to the second buffer at the subsequent stage or the preceding stage; and a control signal generation unit for generating a control signal for controlling a common-mode voltage of the first buffer according to a difference voltage between an output of the first reference voltage generation unit and an output of the second reference voltage generation unit, and giving the control signal to the first buffer and first reference voltage generation unit.

    Abstract translation: 一种共模电压控制器,用于在信号传输电路中的第一缓冲器的后级或前一级调节第一缓冲器和第二缓冲器之间的共模电压,包括:第一参考电压产生单元,用于产生公共 - 对应于第一缓冲器的模式电压; 第二参考电压产生单元,用于在后级或前一级产生对应于第二缓冲器的共模电压; 以及控制信号生成单元,用于根据第一参考电压产生单元的输出与第二参考电压产生单元的输出之间的差电压产生用于控制第一缓冲器的共模电压的控制信号,并且给出 到第一缓冲器和第一参考电压产生单元的控制信号。

    SCHALTUNGSANORDNUNG UND VERFAHREN ZUM ERZEUGEN VON STEUERSIGNALEN FÜR AUF EINEM HOHEN BEZUGSPOTENTIAL LIEGENDE KOMPONENTEN
    7.
    发明公开
    SCHALTUNGSANORDNUNG UND VERFAHREN ZUM ERZEUGEN VON STEUERSIGNALEN FÜR AUF EINEM HOHEN BEZUGSPOTENTIAL LIEGENDE KOMPONENTEN 有权
    电路装置和方法产生控制信号有关的高潜力COVER水平分量

    公开(公告)号:EP1917711A2

    公开(公告)日:2008-05-07

    申请号:EP06762140.9

    申请日:2006-06-22

    CPC classification number: H02M1/08 H02M7/538 H03K5/003 H03K17/6871 H05B41/2828

    Abstract: In a circuit (1) for producing or transmitting control signals (Q) for a current inverter (2) comprising at least one first switch (Shigh) with a high potential and a second switch (Slow) with a low potential, a connection point between the two switches (Shigh, Slow) forms the output of the current inverter (2). The circuit (1) also comprises a capacitor (Ccap) which a) is connected to the output of the current inverter (2) in a first operating phase by means of switching elements (S1-S4), in such a way that it enables a current flow in a state wherein the two switches (Shigh/ Slow) of the current inverter (2) are open, and b) is connected to the current inverter output in a second operating phase by means of the switching elements (S1-S4) with high impedance, such that a control signal (Q) applied to a side of the capacitor (Ccap) by a control device is transformed into a higher potential.

    SHIFT RESISTOR AND METHOD FOR DRIVING SAME
    8.
    发明公开
    SHIFT RESISTOR AND METHOD FOR DRIVING SAME 有权
    Pegelschieberschaltung zur Verwendung在einem Schieberegister

    公开(公告)号:EP1575167A1

    公开(公告)日:2005-09-14

    申请号:EP03780762.5

    申请日:2003-12-15

    Abstract: A low power consumption shift register which inputs a CK signal with a low voltage with almost no effect of variation in characteristics of transistors. In the invention, an input portion of an inverter is set at a threshold voltage thereof and a CK signal is inputted to the input portion of the inverter through a capacitor means. In this manner, the CK signal is amplified, which is sent to the shift register. That is, by obtaining the threshold potential of the inverter, the shift register which operates with almost no effect of variation in characteristics of transistors can be provided.

    Abstract translation: 低功耗移位寄存器,其输入具有低电压的CK信号,几乎不影响晶体管的特性变化。 在本发明中,将逆变器的输入部设定为阈值电压,通过电容器装置将CK信号输入到逆变器的输入部。 以这种方式,CK信号被放大,发送到移位寄存器。 也就是说,通过获得反相器的阈值电位,可以提供几乎不会影响晶体管特性变化的移位寄存器。

    High-speed burst-mode opto-electronic receiver
    10.
    发明公开
    High-speed burst-mode opto-electronic receiver 审中-公开
    爆炸模式(OpstelektronischerHochgeschwindigkeitsempfängermit Burst-Modus)

    公开(公告)号:EP1361684A1

    公开(公告)日:2003-11-12

    申请号:EP02253222.0

    申请日:2002-05-08

    Abstract: The invention relates to a burst receiver for receiving an optical burst-mode signal (1), comprising signals with different power levels, originating from different senders. The burst receiver (10) comprises first conversion means (13, 14), that are arranged for receiving the input signal (1) and providing an inverted and a non-inverted optical signal (5, 4). These inverted and non-inverted optical signals (5, 4) are applied to a balanced receiver (6). The balanced receiver (10) provides an electrical output signal (9) corresponding to the difference between the inverted and non-inverted optical signal (5, 4).

    Abstract translation: 本发明涉及一种用于接收光突发模式信号(1)的脉冲串接收器,其包括源自不同发送器的具有不同功率电平的信号。 突发接收器(10)包括第一转换装置(13,14),其被布置用于接收输入信号(1)并提供反相和非反相光信号(4,5)。 这些反相和非反相光信号(5,4)被施加到平衡接收器(6)。 平衡式接收器(10)提供对应于反相和非反相光信号(4,5)之间的差的电输出信号(9)。

Patent Agency Ranking