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    CODING RATE MATCHING PROCESSING METHOD AND DEVICE
    3.
    发明公开
    CODING RATE MATCHING PROCESSING METHOD AND DEVICE 审中-公开
    VERFAHREN UND VORRICHTUNG ZUR CODIERUNGSRATENANPASSUNGSVERARBEITUNG

    公开(公告)号：EP3098970A4

    公开(公告)日：2017-07-05

    申请号：EP14883364

    申请日：2014-02-20

    申请人： HUAWEI TECH CO LTD

    发明人： CHEN JUN ,  LI BIN ,  SHEN HUI

    IPC分类号： H03M13/00 ,  H03M13/13 ,  H04L1/18

    CPC分类号： H03M13/13 ,  H03M13/6306 ,  H03M13/6356 ,  H03M13/6362 ,  H04L1/18

    摘要： A rate matching processing method and apparatus for coding are disclosed. The method includes: dividing coded bits output by a Polar encoder into M groups, and performing interleaving processing on coded bits in the 1 st group to the M th group separately, where M is a positive integer; performing bit reduction processing on coded bits in multiple groups of the M groups according to a size of a virtual IR buffer module, coding bits, on which the reduction processing is performed, in first groups of the 1 st group to the M th group, outputting the coded bits to the virtual IR buffer module, and discarding coded bits in last groups of the 1 st group to the M th group; comparing a quantity of available bits of a transmission channel with a quantity of coded bits, in multiple groups, stored in the virtual IR buffer module, and performing, according to a comparison result, repetition or reduction processing on the coded bits, in the multiple groups, stored in the virtual IR buffer module; and performing tandem processing on coded bits on which the repetition or reduction processing is performed, to generate one bit stream, and sending the bit stream through the transmission channel.

    摘要翻译： 公开了一种用于编码的速率匹配处理方法和设备。 该方法包括：将Polar编码器输出的编码比特划分为M组，并将第一组编码比特分别进行交织处理至第M组，其中M为正整数; 根据虚拟IR缓存模块的大小，所述第一组到第M组中的第一组上执行缩小处理的编码比特，对所述M组中的多组编码比特进行比特缩减处理， 将编码的比特输出到虚拟IR缓存模块，丢弃第一组最后一组到第M组的编码比特; 将传输信道的可用比特数量与存储在虚拟IR缓冲器模块中的多个组中的编码比特的数量进行比较，并且根据比较结果对编码比特执行重复或缩减处理， 组，存储在虚拟IR缓冲模块中; 对执行了重复或者缩小处理的编码比特进行汇接处理，生成一个比特流，并通过传输通道发送。

    DATA PROCESSING METHOD AND SYSTEM BASED ON QUASI-CYCLIC LDPC
    5.
    发明公开
    DATA PROCESSING METHOD AND SYSTEM BASED ON QUASI-CYCLIC LDPC 审中-公开
    日期：年月日

    公开(公告)号：EP3182601A1

    公开(公告)日：2017-06-21

    申请号：EP15875055

    申请日：2015-12-07

    申请人： HUAWEI TECH CO LTD

    发明人： ZENG YANXING ,  SHEN JIANQIANG

    IPC分类号： H03M13/11

    CPC分类号： H03M13/116 ,  G06F11/1044 ,  G06F2212/1036 ,  H03M13/6356 ,  H03M13/6516

    摘要： The present invention discloses a data processing method and system based on a quasi-cyclic LDPC, where the method includes: calculating a magnitude of an information bit of the quasi-cyclic LDPC (S101); obtaining service data having the same size as service data space in a storage unit (S102); when the size of the service data is less than the magnitude of the information bit of the quasi-cyclic LDPC, calculating a difference value between the magnitude of the information bit of the quasi-cyclic LDPC and the size of the service data, and filling the service data with the same amount of known data as the difference value (S103); coding the filled service data to obtain redundancy check data corresponding to the service data (S104); and sending the service data and the redundancy check data to a corresponding physical location in the storage unit (S105). The solution can ensure that when a code length of the quasi-cyclic LDPC is constant, the code length ideally adapts to internal space of the storage unit, and the quasi-cyclic LDPC has a relatively high error correction capability, thereby improving reliability and service life of the storage unit.

    摘要翻译： 本发明公开了一种基于准循环LDPC的数据处理方法和系统，其中所述方法包括：计算准循环LDPC的信息比特的大小（S101）; 获取与存储单元中的服务数据空间相同大小的服务数据（S102）; 当服务数据的大小小于准循环LDPC的信息比特大小时，计算准循环LDPC的信息比特大小与服务数据的大小之间的差值，然后填充 具有与差值相同量的已知数据的服务数据（S103）; 对填充的服务数据进行编码以获得与服务数据相对应的冗余校验数据（S104）; 以及将所述服务数据和所述冗余校验数据发送到所述存储单元中的相应物理位置（S105）。 该解决方案可以确保当准循环LDPC的码长恒定时，码长度理想地适应存储单元的内部空间，并且准循环LDPC具有较高的纠错能力，从而提高可靠性和服务性 存储单元的寿命。

    A data communication system and rate matching method
    6.
    发明公开
    A data communication system and rate matching method 审中-公开
    数据通信系统和速率匹配方法

    公开(公告)号：EP2019503A3

    公开(公告)日：2017-05-17

    申请号：EP08016303.3

    申请日：2000-07-06

    申请人： Samsung Electronics Co., Ltd.

    发明人： Kim, Min-Goo ,  Kim, Beong-Jo ,  Kim, Se-Hyoung ,  Choi, Soon-Jae ,  Lee, Young-Hwan

    IPC分类号： H04L12/00 ,  H03M13/29 ,  H03M13/00 ,  H04L1/00

    CPC分类号： H04L1/0041 ,  H03M13/2957 ,  H03M13/2993 ,  H03M13/6356 ,  H03M13/6362 ,  H03M13/6513 ,  H03M13/6569 ,  H04L1/0059 ,  H04L1/0066 ,  H04L1/0069 ,  H04L1/08

    摘要： A data communication system and a rate matching method to be applied in such data communication system are disclosed. It is possible to use one or both of a non-systematic code (such as a convolutional code or linear block code) and a systematic code (such as a turbo code). According to one aspect, the data communication system comprises a rate matching means with first to third rate matching means for receiving systematic bit stream, first parity bit stream, and second parity bit stream. At least one of the rate matching means rate matches a determined number of parity bits in a respective parity bit stream and a part of the encoded bits are rate matched in each of the rate matching means respectively, and can be controlled according to rate matching parameters. Corresponding bits to be rate matched among the encoded bits are controlled by a subtraction function.

    摘要翻译： 公开了将在这种数据通信系统中应用的数据通信系统和速率匹配方法。 可以使用非系统代码（例如卷积码或线性分组代码）和系统代码（例如turbo码）中的一种或两种。 根据一个方面，数据通信系统包括具有第一至第三速率匹配装置的速率匹配装置，用于接收系统比特流，第一奇偶校验比特流和第二奇偶校验比特流。 速率匹配装置速率中的至少一个速率匹配装置速率与相应奇偶校验比特流中的确定数量的奇偶校验比特相匹配，并且一部分编码比特分别在每个速率匹配装置中速率匹配，并且可以根据速率匹配参数 。 在编码比特之间速率匹配的相应比特由减法函数控制。

    ENCODER, DECODER, TRANSMISSION APPARATUS AND RECEPTION APPARATUS
    8.
    发明公开
    ENCODER, DECODER, TRANSMISSION APPARATUS AND RECEPTION APPARATUS 有权
    CODEERER，DECODIERER，ÜBERTRAGUNGSVORRICHTUNGUND EMPFANGSVORRICHTUNG

    公开(公告)号：EP3070850A1

    公开(公告)日：2016-09-21

    申请号：EP14862342.4

    申请日：2014-11-13

    申请人： Nippon Hoso Kyokai

    发明人： SUZUKI, Youichi ,  HASHIMOTO, Akinori ,  TANAKA, Shoji ,  TSUCHIDA, Kenichi ,  KIMURA, Takeshi ,  MATSUSAKI, Yoshifumi

    IPC分类号： H03M13/19 ,  H03M13/25 ,  H03M13/27

    CPC分类号： H03M13/1177 ,  H03M13/036 ,  H03M13/1102 ,  H03M13/1165 ,  H03M13/152 ,  H03M13/255 ,  H03M13/2792 ,  H03M13/2906 ,  H03M13/616 ,  H03M13/6356 ,  H04L1/00 ,  H04L1/0041 ,  H04L1/0045 ,  H04L1/0057 ,  H04L1/0071

    摘要： A transmission device and reception device for digital data that have excellent resistance to noise are provided. An encoder (11-1) of this disclosure, included in a transmission device (1) of this disclosure, applies LDPC encoding to digital data using a unique check matrix for each code rate by using a check matrix in which, taking a check matrix initial value table established in advance for each code rate at a code length of 44880 bits as initial values, 1 entries of a partial matrix corresponding to an information length appropriate for a code rate of 93/120 are allocated in the column direction over a cycle of 374 columns. A demodulator (23) of this disclosure, included in a reception device (2) of this disclosure, decodes digital data encoded by the encoder (11-1).

    摘要翻译： 提供了具有优异的耐噪声性的用于数字数据的传输装置和接收装置。 包含在本公开的发送装置（1）中的本公开的编码器（11-1）使用对于每个码率的唯一校验矩阵，使用校验矩阵对LDPC数字数据应用LDPC编码，其中，采用校验矩阵 以44880位的代码长度作为初始值的每个代码率预先建立的初始值表，对应于93/120码率的信息长度的部分矩阵的1个条目在一个周期的列方向上被分配 的374列。 包含在本公开的接收装置（2）中的本公开的解调器（23）对由编码器（11-1）编码的数字数据进行解码。